Changeset 196 for branches/virtcpu varint/UMachine.pas
- Timestamp:
- Sep 22, 2019, 7:13:15 PM (5 years ago)
- Location:
- branches/virtcpu varint
- Files:
-
- 2 edited
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- Unmodified
- Added
- Removed
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branches/virtcpu varint
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Property svn:ignore
set to
lib
virtcpu
virtcpu.lps
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Property svn:ignore
set to
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branches/virtcpu varint/UMachine.pas
r195 r196 1 1 unit UMachine; 2 3 2 4 3 {$mode delphi}{$H+} … … 85 84 procedure OpcodeLddr; 86 85 public 86 Memory: Pointer; 87 87 Registers: array of T; 88 88 IP: T; 89 SP: T; 89 90 Condition: Boolean; 90 SP: T;91 Memory: array of Byte;92 91 Terminated: Boolean; 93 92 Ticks: Integer; 94 93 procedure Start; 95 94 procedure Stop; 95 procedure Step; inline; 96 96 constructor Create(AOwner: TComponent); override; 97 97 published … … 100 100 end; 101 101 102 { TMachine } 103 104 TMachine = class(TComponent) 105 private 106 FMemorySize: Integer; 107 procedure SetMemorySize(AValue: Integer); 108 public 109 Cpu: TCpu; 110 Memory: Pointer; 111 property MemorySize: Integer read FMemorySize write SetMemorySize; 112 constructor Create(AOwner: TComponent); override; 113 destructor Destroy; override; 114 end; 115 102 116 103 117 implementation 104 118 119 { TMachine } 120 121 procedure TMachine.SetMemorySize(AValue: Integer); 122 begin 123 if FMemorySize = AValue then Exit; 124 FMemorySize := AValue; 125 Memory := ReAllocMem(Memory, FMemorySize); 126 Cpu.Memory := Memory; 127 end; 128 129 constructor TMachine.Create(AOwner: TComponent); 130 begin 131 inherited; 132 Cpu := TCpu.Create(nil); 133 MemorySize := 1000; 134 end; 135 136 destructor TMachine.Destroy; 137 begin 138 MemorySize := 0; 139 FreeAndNil(Cpu); 140 inherited Destroy; 141 end; 142 105 143 { TCPU } 106 144 107 145 function TCPU.ReadNext: T; 108 146 begin 109 IP := IP + Result.ReadFromAddr( @Memory[IP]);147 IP := IP + Result.ReadFromAddr(Pointer(NativeUInt(Memory) + IP)); 110 148 end; 111 149 … … 147 185 P1 := ReadNext; 148 186 P2 := ReadNext; 149 Registers[P1] := Memory[Registers[P2]];187 Registers[P1].ReadFromAddr(Pointer(NativeUInt(Memory) + Integer(Registers[P2]))); 150 188 end; 151 189 … … 157 195 P1 := ReadNext; 158 196 P2 := ReadNext; 159 Memory[Registers[P1]] := Registers[P2];197 Registers[P2].WriteToAddr(Pointer(NativeUInt(Memory) + Registers[P1])); 160 198 end; 161 199 … … 307 345 P1 := ReadNext; 308 346 SP := SP - Registers[P1].GetByteSize; 309 Registers[P1].WriteToAddr( @Memory[SP]);347 Registers[P1].WriteToAddr(Pointer(NativeUInt(Memory) + Integer(SP))); 310 348 end; 311 349 312 350 procedure TCPU.OpcodePop; 313 351 begin 314 SP := SP + Registers[ReadNext].ReadFromAddr( @Memory[SP]);352 SP := SP + Registers[ReadNext].ReadFromAddr(Pointer(NativeUInt(Memory) + Integer(SP))); 315 353 end; 316 354 … … 321 359 Addr := ReadNext; 322 360 SP := SP - IP.GetByteSize; 323 IP.WriteToAddr( @Memory[SP]);361 IP.WriteToAddr(Pointer(NativeUInt(Memory) + SP)); 324 362 IP := Addr; 325 363 end; … … 331 369 Addr := ReadNext; 332 370 SP := SP - IP.GetByteSize; 333 IP.WriteToAddr( @Memory[SP]);371 IP.WriteToAddr(Pointer(NativeUInt(Memory) + SP)); 334 372 IP := IP + Addr; 335 373 end; 336 374 337 375 procedure TCPU.OpcodeReturn; 338 var 339 S: Integer; 340 begin 341 SP := SP + IP.ReadFromAddr(@Memory[SP]); 376 begin 377 SP := SP + IP.ReadFromAddr(Pointer(NativeUInt(Memory) + SP)); 342 378 end; 343 379 … … 424 460 Src: T; 425 461 Dst: T; 426 Size: T; 462 Count: T; 463 Bytes: T; 427 464 begin 428 465 Src := ReadNext; 429 466 Dst := ReadNext; 430 Size := ReadNext; 431 while Registers[Size] > 0 do begin 432 Memory[Registers[Dst]] := Memory[Registers[Src]]; 433 Inc(Registers[Src]); 434 Inc(Registers[Dst]); 435 Dec(Registers[Size]); 467 Count := ReadNext; 468 Bytes := ReadNext; 469 while Registers[Count] > 0 do begin 470 Move(Pointer(NativeUInt(Memory) + Registers[Src])^, 471 Pointer(NativeUInt(Memory) + Registers[Dst])^, Bytes); 472 Inc(Registers[Src], Bytes); 473 Inc(Registers[Dst], Bytes); 474 Dec(Registers[Count]); 436 475 end; 437 476 end; … … 441 480 Src: T; 442 481 Dst: T; 443 Size: T; 482 Count: T; 483 Bytes: T; 444 484 begin 445 485 Src := ReadNext; 446 486 Dst := ReadNext; 447 Size := ReadNext; 448 while Registers[Size] > 0 do begin 449 Memory[Registers[Dst]] := Memory[Registers[Src]]; 450 Dec(Registers[Src]); 451 Dec(Registers[Dst]); 452 Dec(Registers[Size]); 487 Count := ReadNext; 488 Bytes := ReadNext; 489 while Registers[Count] > 0 do begin 490 Move(Pointer(NativeUInt(Memory) + Registers[Src])^, 491 Pointer(NativeUInt(Memory) + Registers[Dst])^, Bytes); 492 Dec(Registers[Src], Bytes); 493 Dec(Registers[Dst], Bytes); 494 Dec(Registers[Count]); 453 495 end; 454 496 end; 455 497 456 498 procedure TCPU.Start; 457 var458 Opcode: T;459 499 begin 460 500 Terminated := False; 461 501 Ticks := 0; 462 502 IP := 0; 463 SP := Length(Memory); 464 while not Terminated do begin 465 Opcode := ReadNext; 466 if (Opcode >= 0) and (Opcode <= T(Integer(High(TOpcode)))) then 467 OpcodeHandlers[TOpcode(Byte(Opcode))] 468 else raise Exception.Create(Format('Unsupported instruction %d', [Int64(Opcode)])); 469 Inc(Ticks); 470 end; 503 SP := MemSize(Memory); 504 while not Terminated do 505 Step; 471 506 end; 472 507 … … 474 509 begin 475 510 Terminated := True; 511 end; 512 513 procedure TCPU.Step; 514 var 515 Opcode: T; 516 begin 517 Opcode := ReadNext; 518 if (Opcode >= 0) and (Opcode <= T(Integer(High(TOpcode)))) then 519 OpcodeHandlers[TOpcode(Byte(Opcode))] 520 else raise Exception.Create(Format('Unsupported instruction %d on address %x', [Int64(Opcode), Int64(IP)])); 521 Inc(Ticks); 476 522 end; 477 523 … … 480 526 inherited; 481 527 SetLength(Registers, 16); 482 SetLength(Memory, 1024);483 528 OpcodeHandlers[opNop] := OpcodeNop; 484 529 OpcodeHandlers[opHalt] := OpcodeHalt;
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