Changeset 181 for branches/virtualcpu4/UCpu.pas

Timestamp:

Apr 13, 2019, 12:03:31 AM (6 years ago)

Author:

chronos

Message:

• Added: Disassemble instruction.

File:

• branches/virtualcpu4/UCpu.pas (modified) (1 diff)

branches/virtualcpu4/UCpu.pas

@@ -134 +134 @@
   end;
 
+  TOpcodeParam = (prNone, prReg, prData, prAddr, prAddrRel);
+  TOpcodeDef = record
+    Name: string;
+    Param1: TOpcodeParam;
+    Param2: TOpcodeParam;
+    Param3: TOpcodeParam;
+  end;
+
 const
   BitWidthBytes: array[TBitWidth] of Byte = (0, 1, 2, 4, 8);
   BitWidthText: array[TBitWidth] of string = ('None', '8-bit', '16-bit', '32-bit', '64-bit');
+  OpcodeDef: array[TOpcode] of TOpcodeDef = (
+    (Name: 'NOP'; Param1: prNone; Param2: prNone; Param3: prNone),
+    (Name: 'HALT'; Param1: prNone; Param2: prNone; Param3: prNone),
+    (Name: 'LD'; Param1: prReg; Param2: prReg; Param3: prNone),
+    (Name: 'LDI'; Param1: prReg; Param2: prData; Param3: prNone),
+    (Name: 'JP'; Param1: prAddr; Param2: prNone; Param3: prNone),
+    (Name: 'JPZ'; Param1: prAddr; Param2: prNone; Param3: prNone),
+    (Name: 'JPNZ'; Param1: prAddr; Param2: prNone; Param3: prNone),
+    (Name: 'JR'; Param1: prAddrRel; Param2: prNone; Param3: prNone),
+    (Name: 'JRZ'; Param1: prAddrRel; Param2: prNone; Param3: prNone),
+    (Name: 'JRNZ'; Param1: prAddrRel; Param2: prNone; Param3: prNone),
+    (Name: 'NEG'; Param1: prReg; Param2: prNone; Param3: prNone),
+    (Name: 'CLR'; Param1: prReg; Param2: prNone; Param3: prNone),
+    (Name: 'LDM'; Param1: prReg; Param2: prReg; Param3: prNone),
+    (Name: 'STM'; Param1: prReg; Param2: prReg; Param3: prNone),
+    (Name: 'EX'; Param1: prReg; Param2: prReg; Param3: prNone),
+    (Name: 'PUSH'; Param1: prReg; Param2: prNone; Param3: prNone),
+    (Name: 'POP'; Param1: prReg; Param2: prNone; Param3: prNone),
+    (Name: 'CALL'; Param1: prAddr; Param2: prNone; Param3: prNone),
+    (Name: 'RET'; Param1: prNone; Param2: prNone; Param3: prNone),
+    (Name: 'ADD'; Param1: prReg; Param2: prReg; Param3: prNone),
+    (Name: 'ADDI'; Param1: prReg; Param2: prData; Param3: prNone),
+    (Name: 'SUB'; Param1: prReg; Param2: prReg; Param3: prNone),
+    (Name: 'SUBI'; Param1: prReg; Param2: prData; Param3: prNone),
+    (Name: 'INC'; Param1: prReg; Param2: prNone; Param3: prNone),
+    (Name: 'DEC'; Param1: prReg; Param2: prNone; Param3: prNone),
+    (Name: 'IN'; Param1: prReg; Param2: prAddr; Param3: prNone),
+    (Name: 'OUT'; Param1: prAddr; Param2: prReg; Param3: prNone),
+    (Name: 'SHL'; Param1: prReg; Param2: prReg; Param3: prNone),
+    (Name: 'SHR'; Param1: prReg; Param2: prReg; Param3: prNone),
+    (Name: 'DP8'; Param1: prNone; Param2: prNone; Param3: prNone),
+    (Name: 'DP16'; Param1: prNone; Param2: prNone; Param3: prNone),
+    (Name: 'DP32'; Param1: prNone; Param2: prNone; Param3: prNone),
+    (Name: 'DP64'; Param1: prNone; Param2: prNone; Param3: prNone),
+    (Name: 'DS'; Param1: prNone; Param2: prNone; Param3: prNone),
+    (Name: 'AS'; Param1: prNone; Param2: prNone; Param3: prNone),
+    (Name: 'TEST'; Param1: prReg; Param2: prNone; Param3: prNone),
+    (Name: 'AND'; Param1: prReg; Param2: prReg; Param3: prNone),
+    (Name: 'OR'; Param1: prReg; Param2: prReg; Param3: prNone),
+    (Name: 'XOR'; Param1: prReg; Param2: prReg; Param3: prNone),
+    (Name: 'LDDR'; Param1: prReg; Param2: prReg; Param3: prReg),
+    (Name: 'LDDR'; Param1: prReg; Param2: prReg; Param3: prReg),
+    (Name: 'MUL'; Param1: prReg; Param2: prReg; Param3: prNone),
+    (Name: 'DIV'; Param1: prReg; Param2: prReg; Param3: prNone),
+    (Name: 'MOD'; Param1: prReg; Param2: prReg; Param3: prNone),
+    (Name: 'AP8'; Param1: prNone; Param2: prNone; Param3: prNone),
+    (Name: 'AP16'; Param1: prNone; Param2: prNone; Param3: prNone),
+    (Name: 'AP32'; Param1: prNone; Param2: prNone; Param3: prNone),
+    (Name: 'AP64'; Param1: prNone; Param2: prNone; Param3: prNone)
+  );
 
 implementation