Ignore:
Timestamp:
Apr 12, 2019, 1:34:47 AM (6 years ago)
Author:
chronos
Message:
  • Added: Drawing to video memory.
File:
1 edited

Legend:

Unmodified
Added
Removed
  • branches/virtualcpu4/UCpu.pas

    r174 r175  
    153153
    154154procedure TCpu.InstLoadImmediate;
    155 begin
    156   case DataSize of
    157     bw8: Registers[Read8].B := Read8;
    158     bw16: Registers[Read8].W := Read16;
    159     bw32: Registers[Read8].D := Read32;
    160     bw64: Registers[Read8].Q := Read64;
     155var
     156  R: TRegIndex;
     157begin
     158  R := Read8;
     159  case DataSize of
     160    bw8: Registers[R].B := Read8;
     161    bw16: Registers[R].W := Read16;
     162    bw32: Registers[R].D := Read32;
     163    bw64: Registers[R].Q := Read64;
    161164  end;
    162165end;
     
    219222
    220223procedure TCpu.InstLoadMem;
    221 begin
    222   case DataSize of
    223     bw8: Registers[Read8].B := PByte(Memory + PAddress(@Registers[Read8])^)^;
    224     bw16: Registers[Read8].W := PWord(Memory + PAddress(@Registers[Read8])^)^;
    225     bw32: Registers[Read8].D := PDWord(Memory + PAddress(@Registers[Read8])^)^;
    226     bw64: Registers[Read8].Q := PQWord(Memory + PAddress(@Registers[Read8])^)^;
     224var
     225  R1, R2: TRegIndex;
     226begin
     227  R1 := Read8;
     228  R2 := Read8;
     229  case AddressSize of
     230    bw8: case DataSize of
     231      bw8: Registers[R1].B := PByte(Memory + PByte(@Registers[R2])^)^;
     232      bw16: Registers[R1].W := PWord(Memory + PByte(@Registers[R2])^)^;
     233      bw32: Registers[R1].D := PDWord(Memory + PByte(@Registers[R2])^)^;
     234      bw64: Registers[R1].Q := PQWord(Memory + PByte(@Registers[R2])^)^;
     235    end;
     236    bw16: case DataSize of
     237      bw8: Registers[R1].B := PByte(Memory + PWord(@Registers[R2])^)^;
     238      bw16: Registers[R1].W := PWord(Memory + PWord(@Registers[R2])^)^;
     239      bw32: Registers[R1].D := PDWord(Memory + PWord(@Registers[R2])^)^;
     240      bw64: Registers[R1].Q := PQWord(Memory + PWord(@Registers[R2])^)^;
     241    end;
     242    bw32: case DataSize of
     243      bw8: Registers[R1].B := PByte(Memory + PDWord(@Registers[R2])^)^;
     244      bw16: Registers[R1].W := PWord(Memory + PDWord(@Registers[R2])^)^;
     245      bw32: Registers[R1].D := PDWord(Memory + PDWord(@Registers[R2])^)^;
     246      bw64: Registers[R1].Q := PQWord(Memory + PDWord(@Registers[R2])^)^;
     247    end;
     248    bw64: case DataSize of
     249      bw8: Registers[R1].B := PByte(Memory + PQWord(@Registers[R2])^)^;
     250      bw16: Registers[R1].W := PWord(Memory + PQWord(@Registers[R2])^)^;
     251      bw32: Registers[R1].D := PDWord(Memory + PQWord(@Registers[R2])^)^;
     252      bw64: Registers[R1].Q := PQWord(Memory + PQWord(@Registers[R2])^)^;
     253    end;
    227254  end;
    228255end;
    229256
    230257procedure TCpu.InstStoreMem;
    231 begin
    232   case DataSize of
    233     bw8: PByte(Memory + PAddress(@Registers[Read8])^)^ := Registers[Read8].B;
    234     bw16: PWord(Memory + PAddress(@Registers[Read8])^)^ := Registers[Read8].W;
    235     bw32: PDWord(Memory + PAddress(@Registers[Read8])^)^ := Registers[Read8].D;
    236     bw64: PQWord(Memory + PAddress(@Registers[Read8])^)^ := Registers[Read8].Q;
     258var
     259  R1, R2: TRegIndex;
     260begin
     261  R1 := Read8;
     262  R2 := Read8;
     263  case AddressSize of
     264    bw8: case DataSize of
     265      bw8: PByte(Memory + PByte(@Registers[R1])^)^ := Registers[R2].B;
     266      bw16: PWord(Memory + PByte(@Registers[R1])^)^ := Registers[R2].W;
     267      bw32: PDWord(Memory + PByte(@Registers[R1])^)^ := Registers[R2].D;
     268      bw64: PQWord(Memory + PByte(@Registers[R1])^)^ := Registers[R2].Q;
     269    end;
     270    bw16: case DataSize of
     271      bw8: PByte(Memory + PWord(@Registers[R1])^)^ := Registers[R2].B;
     272      bw16: PWord(Memory + PWord(@Registers[R1])^)^ := Registers[R2].W;
     273      bw32: PDWord(Memory + PWord(@Registers[R1])^)^ := Registers[R2].D;
     274      bw64: PQWord(Memory + PWord(@Registers[R1])^)^ := Registers[R2].Q;
     275    end;
     276    bw32: case DataSize of
     277      bw8: PByte(Memory + PDWord(@Registers[R1])^)^ := Registers[R2].B;
     278      bw16: PWord(Memory + PDWord(@Registers[R1])^)^ := Registers[R2].W;
     279      bw32: PDWord(Memory + PDWord(@Registers[R1])^)^ := Registers[R2].D;
     280      bw64: PQWord(Memory + PDWord(@Registers[R1])^)^ := Registers[R2].Q;
     281    end;
     282    bw64: case DataSize of
     283      bw8: PByte(Memory + PQWord(@Registers[R1])^)^ := Registers[R2].B;
     284      bw16: PWord(Memory + PQWord(@Registers[R1])^)^ := Registers[R2].W;
     285      bw32: PDWord(Memory + PQWord(@Registers[R1])^)^ := Registers[R2].D;
     286      bw64: PQWord(Memory + PQWord(@Registers[R1])^)^ := Registers[R2].Q;
     287    end;
    237288  end;
    238289end;
     
    436487procedure TCpu.InstDec;
    437488var
    438   R1: TRegIndex;
    439 begin
    440   R1 := Read8;
    441   case DataSize of
    442     bw8: Registers[R1].B := Registers[R1].B - 1;
    443     bw16: Registers[R1].W := Registers[R1].W - 1;
    444     bw32: Registers[R1].D := Registers[R1].D - 1;
    445     bw64: Registers[R1].Q := Registers[R1].Q - 1;
     489  R: TRegIndex;
     490begin
     491  R := Read8;
     492  case DataSize of
     493    bw8: Registers[R].B := Registers[R].B - 1;
     494    bw16: Registers[R].W := Registers[R].W - 1;
     495    bw32: Registers[R].D := Registers[R].D - 1;
     496    bw64: Registers[R].Q := Registers[R].Q - 1;
    446497  end;
    447498end;
     
    450501begin
    451502  case AddressSize of
    452     bw8: if Z then IP := Read8;
    453     bw16: if Z then IP := Read16;
    454     bw32: if Z then IP := Read32;
    455     bw64: if Z then IP := Read64;
     503    bw8: if Z then IP := Read8 else Read8;
     504    bw16: if Z then IP := Read16 else Read16;
     505    bw32: if Z then IP := Read32 else Read32;
     506    bw64: if Z then IP := Read64 else Read64;
    456507  end;
    457508end;
     
    460511begin
    461512  case AddressSize of
    462     bw8: if not Z then IP := Read8;
    463     bw16: if not Z then IP := Read16;
    464     bw32: if not Z then IP := Read32;
    465     bw64: if not Z then IP := Read64;
     513    bw8: if not Z then IP := Read8 else Read8;
     514    bw16: if not Z then IP := Read16 else Read16;
     515    bw32: if not Z then IP := Read32 else Read32;
     516    bw64: if not Z then IP := Read64 else Read64;
    466517  end;
    467518end;
     
    913964    if Assigned(Instructions[TOpcode(Opcode)]) then Instructions[TOpcode(Opcode)]
    914965      else raise Exception.Create('Missing instruction handler for opcode '+ IntToStr(Opcode));
    915   end else raise Exception.Create('Unsupported opcode ' + IntToStr(Opcode) + ' at address ' + IntToHex(IP, 8) + '.');
     966  end else raise Exception.Create('Unsupported opcode ' + IntToStr(Opcode) + ' at address ' + IntToHex(IP - 1, 8) + '.');
    916967  if DataSizeLast <> bwNone then begin
    917968    DataSize := DataSizeLast;
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