Changeset 168


Ignore:
Timestamp:
Oct 16, 2018, 11:03:59 AM (6 years ago)
Author:
chronos
Message:
  • Added: Show CPU tick count.
  • Added: Show IP register value.
  • Modified: Condition instructions store result to R1 register rather then to condition boolean variable.
  • Modified: Shorter InstructionWriter method names.
Location:
branches/virtcpu fixed int
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • branches/virtcpu fixed int/UFormMain.lfm

    r164 r168  
    11object Form1: TForm1
    2   Left = 456
     2  Left = 385
    33  Height = 762
    4   Top = 163
     4  Top = 208
    55  Width = 1286
    66  Caption = 'Form1'
    … …  
    8080    TabOrder = 4
    8181  end
     82  object LabelTicks: TLabel
     83    Left = 16
     84    Height = 20
     85    Top = 612
     86    Width = 35
     87    Caption = 'Ticks:'
     88    ParentColor = False
     89  end
    8290  object Timer1: TTimer
    8391    Interval = 500

  • branches/virtcpu fixed int/UFormMain.pas

    r165 r168  
    1616    Button1: TButton;
    1717    Button2: TButton;
     18    LabelTicks: TLabel;
    1819    ListViewMemory: TListView;
    1920    ListViewRegisters: TListView;
    … …  
    5758var
    5859  LabelStart: Integer;
    59 begin
     60  LabelPrint: Integer;
     61  LabelPrintBack: Integer;
     62  R0: Integer;
     63  R1: Integer;
     64  R2: Integer;
     65  R3: Integer;
     66  R4: Integer;
     67begin
     68  R0 := 0;
     69  R1 := 1;
     70  R2 := 2;
     71  R3 := 3;
     72  R4 := 4;
    6073  with InstructionWriter do begin
    61     {AddNop;
    62     AddLdc(1, $ffff);
    63     AddLd(0, 1);
    64     AddLdc(2, $10);
    65     AddStm(2, 0);
     74    {NoOperation;
     75    LoadConst(1, $ffff);
     76    Load(0, 1);
     77    LoadConst(2, $10);
     78    StoreMemory(2, 0);
    6679    }
    67 
    68     AddLdc(2, 0);
    69     AddLdc(0, 0);
    70     LabelStart := IP;
    71     AddIn(1, 0);
    72     AddOut(0, 1);
    73     AddInc(2);
    74     AddJump(LabelStart);
    75     AddHalt;
     80    LabelPrint := $100;
     81
     82    LoadConst(R2, 0);
     83    LoadConst(R0, 0);
     84    LoadConst(R4, Ord('a'));
     85  LabelStart := IP;
     86    Input(R1, 0);
     87    Output(0, R1);
     88    Subtract(R1, R4);
     89    JumpZero(R1, LabelPrint);
     90  LabelPrintBack := IP;
     91    Increment(R2);
     92    Jump(LabelStart);
     93    Halt;
     94  IP := LabelPrint;
     95    LoadConst(R3, Ord('!'));
     96    Output(0, R3);
     97    Jump(LabelPrintBack)
    7698  end;
    7799end;
    … …  
    122144procedure TForm1.ListViewRegistersData(Sender: TObject; Item: TListItem);
    123145begin
    124   if Item.Index < Length(Cpu.Registers) then begin
    125     Item.Caption := 'R' + IntToStr(Item.Index);
    126     Item.SubItems.Add(IntToHex(Cpu.Registers[Item.Index], 8));
     146  if Item.Index < Length(Cpu.Registers) + 1 then begin
     147    if Item.Index = 0 then begin
     148      Item.Caption := 'IP';
     149      Item.SubItems.Add(IntToHex(Cpu.IP, 8));
     150    end else begin
     151      Item.Caption := 'R' + IntToStr(Item.Index - 1);
     152      Item.SubItems.Add(IntToHex(Cpu.Registers[Item.Index - 1], 8));
     153    end;
    127154  end;
    128155end;
    … …  
    138165  ReloadMemoryDump;
    139166  ReloadRegisterDump;
     167  LabelTicks.Caption := 'Ticks: ' + IntToStr(Cpu.Ticks);
    140168end;
    141169

  • branches/virtcpu fixed int/UInstructionWriter.pas

    r165 r168  
    1717    IP: T;
    1818    procedure Write(Value: T);
    19     procedure AddNop;
    20     procedure AddLd(R1, R2: Integer);
    21     procedure AddHalt;
    22     procedure AddLdc(R, Value: Integer);
    23     procedure AddLdm(R1, R2: Integer);
    24     procedure AddStm(R1, R2: Integer);
    25     procedure AddNeg(R: Integer);
    26     procedure AddIn(R1, R2: Integer);
    27     procedure AddOut(R1, R2: Integer);
    28     procedure AddJump(Addr: Integer);
    29     {$IFDEF EXT_REL_JUMP}procedure AddJr(Addr: Integer);{$ENDIF}
    30     procedure AddInc(R: Integer);
     19    procedure NoOperation;
     20    procedure Load(R1, R2: Integer);
     21    procedure Halt;
     22    procedure LoadConst(R, Value: Integer);
     23    procedure LoadMemory(R1, R2: Integer);
     24    procedure StoreMemory(R1, R2: Integer);
     25    procedure Neg(R: Integer);
     26    procedure Input(R1, R2: Integer);
     27    procedure Output(R1, R2: Integer);
     28    procedure Subtract(R1, R2: Integer);
     29    procedure Jump(Addr: Integer);
     30    procedure JumpNotZero(R1: Integer; Addr: Integer);
     31    procedure JumpZero(R1: Integer; Addr: Integer);
     32    {$IFDEF EXT_REL_JUMP}procedure JumpRelative(Addr: Integer);{$ENDIF}
     33    procedure Increment(R: Integer);
     34    procedure Decrement(R: Integer);
    3135    constructor Create;
    3236  end;
    … …  
    3741{ TInstructionWriter }
    3842
    39 procedure TInstructionWriter.AddNop;
     43procedure TInstructionWriter.NoOperation;
    4044begin
    4145  Write(T(opNop));
    4246end;
    4347
    44 procedure TInstructionWriter.AddLd(R1, R2: Integer);
     48procedure TInstructionWriter.Load(R1, R2: Integer);
    4549begin
    4650  Write(T(opLoad));
    … …  
    4953end;
    5054
    51 procedure TInstructionWriter.AddHalt;
     55procedure TInstructionWriter.Halt;
    5256begin
    5357  Write(T(opHalt));
    5458end;
    5559
    56 procedure TInstructionWriter.AddLdc(R, Value: Integer);
     60procedure TInstructionWriter.LoadConst(R, Value: Integer);
    5761begin
    5862  Write(T(opLoadConst));
    … …  
    6165end;
    6266
    63 procedure TInstructionWriter.AddLdm(R1, R2: Integer);
     67procedure TInstructionWriter.LoadMemory(R1, R2: Integer);
    6468begin
    6569  Write(T(opLoadMem));
    … …  
    6872end;
    6973
    70 procedure TInstructionWriter.AddStm(R1, R2: Integer);
     74procedure TInstructionWriter.StoreMemory(R1, R2: Integer);
    7175begin
    7276  Write(T(opStoreMem));
    … …  
    7579end;
    7680
    77 procedure TInstructionWriter.AddNeg(R: Integer);
     81procedure TInstructionWriter.Neg(R: Integer);
    7882begin
    7983  Write(T(opNeg));
    … …  
    8185end;
    8286
    83 procedure TInstructionWriter.AddIn(R1, R2: Integer);
     87procedure TInstructionWriter.Input(R1, R2: Integer);
    8488begin
    8589  Write(T(opInput));
    … …  
    8892end;
    8993
    90 procedure TInstructionWriter.AddOut(R1, R2: Integer);
     94procedure TInstructionWriter.Output(R1, R2: Integer);
    9195begin
    9296  Write(T(opOutput));
    … …  
    9599end;
    96100
    97 procedure TInstructionWriter.AddJump(Addr: Integer);
     101procedure TInstructionWriter.Subtract(R1, R2: Integer);
     102begin
     103  Write(T(opSub));
     104  Write(R1);
     105  Write(R2);
     106end;
     107
     108procedure TInstructionWriter.Jump(Addr: Integer);
    98109begin
    99110  Write(T(opJump));
    … …  
    101112end;
    102113
     114procedure TInstructionWriter.JumpNotZero(R1: Integer; Addr: Integer);
     115begin
     116  Write(T(opJumpNotZero));
     117  Write(R1);
     118  Write(Addr);
     119end;
     120
     121procedure TInstructionWriter.JumpZero(R1: Integer; Addr: Integer);
     122begin
     123  Write(T(opJumpZero));
     124  Write(R1);
     125  Write(Addr);
     126end;
     127
    103128{$IFDEF EXT_REL_JUMP}
    104 procedure TInstructionWriter.AddJr(Addr: Integer);
     129procedure TInstructionWriter.JumpRelative(Addr: Integer);
    105130begin
    106131  Write(T(opJumpRel));
    … …  
    109134{$ENDIF}
    110135
    111 procedure TInstructionWriter.AddInc(R: Integer);
     136procedure TInstructionWriter.Increment(R: Integer);
    112137begin
    113138  Write(T(opInc));
     139  Write(R);
     140end;
     141
     142procedure TInstructionWriter.Decrement(R: Integer);
     143begin
     144  Write(T(opDec));
    114145  Write(R);
    115146end;

  • branches/virtcpu fixed int/UMachine.pas

    r166 r168  
    55{$DEFINE EXT_ARITHMETIC}
    66{$DEFINE EXT_CONDITIONAL}
    7 //{$DEFINE EXT_LOGICAL}
    8 //{$DEFINE EXT_STACK}
    9 //{$DEFINE EXT_SUBROUTINE}
    10 //{$DEFINE EXT_ROTATION}
    11 //{$DEFINE EXT_MULTIPLICATION}
    12 //{$DEFINE EXT_SHIFT}
    13 //{$DEFINE EXT_BLOCK}
    14 //{$DEFINE EXT_GENERAL}
    15 //{$DEFINE EXT_BIT}
    16 //{$DEFINE EXT_REL_JUMP}
     7{$DEFINE EXT_LOGICAL}
     8{$DEFINE EXT_STACK}
     9{$DEFINE EXT_SUBROUTINE}
     10{$DEFINE EXT_ROTATION}
     11{$DEFINE EXT_MULTIPLICATION}
     12{$DEFINE EXT_SHIFT}
     13{$DEFINE EXT_BLOCK}
     14{$DEFINE EXT_GENERAL}
     15{$DEFINE EXT_BIT}
     16{$DEFINE EXT_REL_JUMP}
    1717
    1818// Extension dependencies
    … …  
    5050    {$IFDEF EXT_STACK}opPush, opPop,{$ENDIF}
    5151    {$IFDEF EXT_CONDITIONAL}
    52     {$IFDEF EXT_REL_JUMP}opJumpRelCond,{$ENDIF}
    53     opJumpCond, opTestEqual, opTestNotEqual, opTestLess,
     52    {$IFDEF EXT_REL_JUMP}opJumpRelZero, opJumpRelNotZero,{$ENDIF}
     53    opJumpZero, opJumpNotZero, opTestEqual, opTestNotEqual, opTestLess,
    5454    opTestLessEqual, opTestGreater, opTestGreaterEqual,
    5555    {$ENDIF}
    … …  
    9797    procedure OpcodeTestLessEqual;
    9898    procedure OpcodeTestLess;
    99     procedure OpcodeJumpCond;
     99    procedure OpcodeJumpCondNotZero;
     100    procedure OpcodeJumpCondZero;
    100101    {$IFDEF EXT_REL_JUMP}
    101     procedure OpcodeJumpRelCond;
     102    procedure OpcodeJumpRelCondNotZero;
     103    procedure OpcodeJumpRelCondZero;
    102104    {$ENDIF}
    103105    {$ENDIF}
    … …  
    141143    Registers: array of T;
    142144    IP: T;
    143     {$IFDEF EXT_CONDITIONAL}
    144     Condition: Boolean;
    145     {$ENDIF}
    146145    {$IFDEF EXT_STACK}
    147146    SP: T;
    … …  
    149148    Memory: array of T;
    150149    Terminated: Boolean;
     150    Ticks: Integer;
    151151    procedure Start;
    152152    procedure Stop;
    … …  
    255255{$IFDEF EXT_CONDITIONAL}
    256256procedure TCPU.OpcodeTestEqual;
    257 begin
    258   Condition := ReadNext = ReadNext;
     257var
     258  P1, P2: T;
     259begin
     260  P1 := ReadNext;
     261  P2 := ReadNext;
     262  if Registers[P1] = Registers[P2] then Registers[P1] := 1
     263    else Registers[P1] := 0;
    259264end;
    260265
    261266procedure TCPU.OpcodeTestNotEqual;
    262 begin
    263   Condition := ReadNext <> ReadNext;
     267var
     268  P1, P2: T;
     269begin
     270  P1 := ReadNext;
     271  P2 := ReadNext;
     272  if Registers[P1] <> Registers[P2] then Registers[P1] := 1
     273    else Registers[P1] := 0;
    264274end;
    265275
    266276procedure TCPU.OpcodeTestGreatEqual;
    267 begin
    268   Condition := ReadNext >= ReadNext;
     277var
     278  P1, P2: T;
     279begin
     280  P1 := ReadNext;
     281  P2 := ReadNext;
     282  if Registers[P1] >= Registers[P2] then Registers[P1] := 1
     283    else Registers[P1] := 0;
    269284end;
    270285
    271286procedure TCPU.OpcodeTestGreat;
    272 begin
    273   Condition := ReadNext > ReadNext;
     287var
     288  P1, P2: T;
     289begin
     290  P1 := ReadNext;
     291  P2 := ReadNext;
     292  if Registers[P1] > Registers[P2] then Registers[P1] := 1
     293    else Registers[P1] := 0;
    274294end;
    275295
    276296procedure TCPU.OpcodeTestLessEqual;
    277 begin
    278   Condition := ReadNext <= ReadNext;
     297var
     298  P1, P2: T;
     299begin
     300  P1 := ReadNext;
     301  P2 := ReadNext;
     302  if Registers[P1] <= Registers[P2] then Registers[P1] := 1
     303    else Registers[P1] := 0;
    279304end;
    280305
    281306procedure TCPU.OpcodeTestLess;
    282 begin
    283   Condition := ReadNext < ReadNext;
    284 end;
    285 
    286 procedure TCPU.OpcodeJumpCond;
    287 begin
    288   if Condition then IP := ReadNext;
    289 end;
    290 
     307var
     308  P1, P2: T;
     309begin
     310  P1 := ReadNext;
     311  P2 := ReadNext;
     312  if Registers[P1] < Registers[P2] then Registers[P1] := 1
     313    else Registers[P1] := 0;
     314end;
     315
     316procedure TCPU.OpcodeJumpCondNotZero;
     317var
     318  P1, P2: T;
     319begin
     320  P1 := ReadNext;
     321  P2 := ReadNext;
     322  if Registers[P1] <> 0 then IP := P2;
     323end;
     324
     325procedure TCPU.OpcodeJumpCondZero;
     326var
     327  P1, P2: T;
     328begin
     329  P1 := ReadNext;
     330  P2 := ReadNext;
     331  if Registers[P1] = 0 then IP := P2;
     332end;
    291333
    292334{$IFDEF EXT_REL_JUMP}
    293 procedure TCPU.OpcodeJumpRelCond;
    294 begin
    295   if Condition then IP := IP + ReadNext;
     335procedure TCPU.OpcodeJumpRelCondZero;
     336var
     337  P1, P2: T;
     338begin
     339  P1 := ReadNext;
     340  P2 := ReadNext;
     341  if P1 = 0 then IP := IP + P2;
     342end;
     343
     344procedure TCPU.OpcodeJumpRelCondNotZero;
     345var
     346  P1, P2: T;
     347begin
     348  P1 := ReadNext;
     349  P2 := ReadNext;
     350  if P1 <> 0 then IP := IP + P2;
    296351end;
    297352{$ENDIF}
    … …  
    503558  Terminated := False;
    504559  IP := 0;
     560  Ticks := 0;
    505561  {$IFDEF EXT_STACK}
    506562  SP := Length(Memory);
    … …  
    511567      OpcodeHandlers[TOpcode(Opcode)]
    512568      else raise Exception.Create(Format('Unsupported instruction %d', [Opcode]));
     569    Inc(Ticks);
    513570  end;
    514571end;
    … …  
    575632  {$ENDIF}
    576633  {$IFDEF EXT_CONDITIONAL}
    577   OpcodeHandlers[opJumpCond] := OpcodeJumpCond;
     634  OpcodeHandlers[opJumpZero] := OpcodeJumpCondZero;
     635  OpcodeHandlers[opJumpNotZero] := OpcodeJumpCondNotZero;
    578636  {$IFDEF EXT_REL_JUMP}
    579   OpcodeHandlers[opJumpRelCond] := OpcodeJumpRelCond;
     637  OpcodeHandlers[opJumpRelZero] := OpcodeJumpRelCondZero;
     638  OpcodeHandlers[opJumpRelNotZero] := OpcodeJumpRelCondNotZero;
    580639  {$ENDIF}
    581640  OpcodeHandlers[opTestEqual] := OpcodeTestEqual;
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