Changeset 157 for branches/virtualcpu3/UMachine.pas
- Timestamp:
- Apr 24, 2018, 11:08:11 AM (7 years ago)
- File:
-
- 1 edited
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branches/virtualcpu3/UMachine.pas (modified) (30 diffs)
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branches/virtualcpu3/UMachine.pas
r156 r157 22 22 TOutputEvent = procedure (Port: T; Value: T) of object; 23 23 TInputEvent = function (Port: T): T of object; 24 PT = ^T; 25 TOpcodeIndex = Byte; 26 POpcodeIndex = ^TOpcodeIndex; 27 TRegIndex = Byte; 28 PRegIndex = ^TRegIndex; 24 29 var 25 30 Terminated: Boolean; 26 31 OpcodeHandlers: array[TOpcode] of TOpcodeHandler; 27 32 function ReadNext: T; 33 function ReadOpcode: TOpcodeIndex; 34 function ReadReg: TRegIndex; 28 35 procedure Step; 29 36 procedure AddOpcode(Opcode: TOpcode; Handler: TOpcodeHandler); … … 51 58 procedure OpcodeLoadMemoryDisplacement; 52 59 procedure OpcodeMultiplication; 53 procedure OpcodeNo p;60 procedure OpcodeNoOperation; 54 61 procedure OpcodeOr; 55 62 procedure OpcodeOutput; … … 67 74 public 68 75 Registers: array of T; 69 Memory: array of T;76 Memory: array of Byte; 70 77 IP: T; 71 78 SP: T; … … 83 90 function TCPU.ReadNext: T; 84 91 begin 85 Result := Memory[IP]; 86 Inc(IP); 92 Result := PT(@Memory[IP])^; 93 Inc(IP, SizeOf(T)); 94 end; 95 96 function TCPU.ReadOpcode: TOpcodeIndex; 97 begin 98 Result := POpcodeIndex(@Memory[IP])^; 99 Inc(IP, SizeOf(TOpcodeIndex)); 100 end; 101 102 function TCPU.ReadReg: TRegIndex; 103 begin 104 Result := PRegIndex(@Memory[IP])^; 105 Inc(IP, SizeOf(TRegIndex)); 87 106 end; 88 107 … … 103 122 end; 104 123 105 procedure TCPU.OpcodeNo p;124 procedure TCPU.OpcodeNoOperation; 106 125 begin 107 126 end; … … 114 133 procedure TCPU.OpcodeLoad; 115 134 var 116 Src, Dest: T ;117 begin 118 Dest := Read Next;119 Src := Read Next;135 Src, Dest: TRegIndex; 136 begin 137 Dest := ReadReg; 138 Src := ReadReg; 120 139 Registers[Dest] := Registers[Src]; 121 140 end; … … 123 142 procedure TCPU.OpcodeLoadConst; 124 143 var 125 Reg: T ;126 begin 127 Reg := Read Next;144 Reg: TRegIndex; 145 begin 146 Reg := ReadReg; 128 147 Registers[Reg] := ReadNext; 129 148 end; … … 131 150 procedure TCPU.OpcodeLoadMemory; 132 151 var 133 Src, Dest: T ;134 begin 135 Dest := Read Next;136 Src := Read Next;137 Registers[Dest] := Memory[Registers[Src]];152 Src, Dest: TRegIndex; 153 begin 154 Dest := ReadReg; 155 Src := ReadReg; 156 Registers[Dest] := PT(@Memory[Registers[Src]])^; 138 157 end; 139 158 140 159 procedure TCPU.OpcodeStoreMemory; 141 160 var 142 Src, Dest: T ;143 begin 144 Dest := Read Next;145 Src := Read Next;146 Memory[Registers[Dest]]:= Registers[Src];161 Src, Dest: TRegIndex; 162 begin 163 Dest := ReadReg; 164 Src := ReadReg; 165 PT(@Memory[Registers[Dest]])^ := Registers[Src]; 147 166 end; 148 167 149 168 procedure TCPU.OpcodeLoadMemoryDisplacement; 150 169 var 151 Reg, Src, Dest: T;152 begin 153 Dest := Read Next;154 Src := Read Next;155 Reg := ReadNext;156 Registers[Dest] := Memory[Registers[Src] + Registers[Reg]];170 Disp, Src, Dest: TRegIndex; 171 begin 172 Dest := ReadReg; 173 Src := ReadReg; 174 Disp := ReadReg; 175 Registers[Dest] := PT(@Memory[Registers[Src] + Registers[Disp]])^; 157 176 end; 158 177 159 178 procedure TCPU.OpcodeStoreMemoryDisplacement; 160 179 var 161 Reg, Src, Dest: T;162 begin 163 Dest := Read Next;164 Reg := ReadNext;165 Src := Read Next;166 Memory[Registers[Dest] + Registers[Reg]]:= Registers[Src];180 Disp, Src, Dest: TRegIndex; 181 begin 182 Dest := ReadReg; 183 Disp := ReadReg; 184 Src := ReadReg; 185 PT(@Memory[Registers[Dest] + Registers[Disp]])^ := Registers[Src]; 167 186 end; 168 187 169 188 procedure TCPU.OpcodeIncrement; 170 189 var 171 Reg: T ;172 begin 173 Reg := Read Next;190 Reg: TRegIndex; 191 begin 192 Reg := ReadReg; 174 193 Registers[Reg] := Registers[Reg] + 1; 175 194 end; … … 177 196 procedure TCPU.OpcodeDecrement; 178 197 var 179 Reg: T ;180 begin 181 Reg := Read Next;198 Reg: TRegIndex; 199 begin 200 Reg := ReadReg; 182 201 Registers[Reg] := Registers[Reg] - 1; 183 202 end; … … 185 204 procedure TCPU.OpcodeAddition; 186 205 var 187 Dest, Src: T ;188 begin 189 Dest := Read Next;190 Src := Read Next;206 Dest, Src: TRegIndex; 207 begin 208 Dest := ReadReg; 209 Src := ReadReg; 191 210 Registers[Dest] := Registers[Dest] + Registers[Src]; 192 211 end; … … 194 213 procedure TCPU.OpcodeSubtraction; 195 214 var 196 Dest, Src: T ;197 begin 198 Dest := Read Next;199 Src := Read Next;215 Dest, Src: TRegIndex; 216 begin 217 Dest := ReadReg; 218 Src := ReadReg; 200 219 Registers[Dest] := Registers[Dest] - Registers[Src]; 201 220 end; … … 203 222 procedure TCPU.OpcodeMultiplication; 204 223 var 205 Dest, Src: T ;206 begin 207 Dest := Read Next;208 Src := Read Next;224 Dest, Src: TRegIndex; 225 begin 226 Dest := ReadReg; 227 Src := ReadReg; 209 228 Registers[Dest] := Registers[Dest] * Registers[Src]; 210 229 end; … … 212 231 procedure TCPU.OpcodeDivision; 213 232 var 214 Dest, Src: T ;215 begin 216 Dest := Read Next;217 Src := Read Next;233 Dest, Src: TRegIndex; 234 begin 235 Dest := ReadReg; 236 Src := ReadReg; 218 237 Registers[Dest] := Registers[Dest] div Registers[Src]; 219 238 end; … … 221 240 procedure TCPU.OpcodeShiftLeft; 222 241 var 223 Dest, Src: T ;224 begin 225 Dest := Read Next;226 Src := Read Next;242 Dest, Src: TRegIndex; 243 begin 244 Dest := ReadReg; 245 Src := ReadReg; 227 246 Registers[Dest] := Registers[Dest] shl Registers[Src]; 228 247 end; … … 230 249 procedure TCPU.OpcodeShiftRight; 231 250 var 232 Src, Dest: T ;233 begin 234 Dest := Read Next;235 Src := Read Next;251 Src, Dest: TRegIndex; 252 begin 253 Dest := ReadReg; 254 Src := ReadReg; 236 255 Registers[Dest] := Registers[Dest] shr Registers[Src]; 237 256 end; … … 239 258 procedure TCPU.OpcodeAnd; 240 259 var 241 Src, Dest: T ;242 begin 243 Dest := Read Next;244 Src := Read Next;260 Src, Dest: TRegIndex; 261 begin 262 Dest := ReadReg; 263 Src := ReadReg; 245 264 Registers[Dest] := Registers[Dest] and Registers[Src]; 246 265 end; … … 248 267 procedure TCPU.OpcodeOr; 249 268 var 250 Src, Dest: T ;251 begin 252 Dest := Read Next;253 Src := Read Next;269 Src, Dest: TRegIndex; 270 begin 271 Dest := ReadReg; 272 Src := ReadReg; 254 273 Registers[Dest] := Registers[Dest] or Registers[Src]; 255 274 end; … … 257 276 procedure TCPU.OpcodeXor; 258 277 var 259 Src, Dest: T ;260 begin 261 Dest := Read Next;262 Src := Read Next;278 Src, Dest: TRegIndex; 279 begin 280 Dest := ReadReg; 281 Src := ReadReg; 263 282 Registers[Dest] := Registers[Dest] xor Registers[Src]; 264 283 end; … … 266 285 procedure TCPU.OpcodeJump; 267 286 var 268 Reg: T ;269 begin 270 Reg := Read Next;287 Reg: TRegIndex; 288 begin 289 Reg := ReadReg; 271 290 IP := Registers[Reg]; 272 291 end; … … 274 293 procedure TCPU.OpcodeJumpConditional; 275 294 var 276 Reg: T ;277 begin 278 Reg := Read Next;295 Reg: TRegIndex; 296 begin 297 Reg := ReadReg; 279 298 if Condition then 280 299 IP := Registers[Reg]; … … 283 302 procedure TCPU.OpcodeJumpRelative; 284 303 var 285 Reg: T ;286 begin 287 Reg := Read Next;304 Reg: TRegIndex; 305 begin 306 Reg := ReadReg; 288 307 IP := IP + Registers[Reg]; 289 308 end; … … 291 310 procedure TCPU.OpcodeJumpRelativeConditional; 292 311 var 293 Reg: T ;294 begin 295 Reg := Read Next;312 Reg: TRegIndex; 313 begin 314 Reg := ReadReg; 296 315 if Condition then 297 316 IP := IP + Registers[Reg]; … … 300 319 procedure TCPU.OpcodePush; 301 320 var 302 Reg: T ;303 begin 304 SP := SP - 1;305 Reg := Read Next;306 Memory[SP]:= Registers[Reg];321 Reg: TRegIndex; 322 begin 323 SP := SP - SizeOf(T); 324 Reg := ReadReg; 325 PT(@Memory[SP])^ := Registers[Reg]; 307 326 end; 308 327 309 328 procedure TCPU.OpcodePop; 310 329 var 311 Reg: T ;312 begin 313 Reg := Read Next;314 Registers[Reg] := Memory[SP];315 SP := SP + 1;330 Reg: TRegIndex; 331 begin 332 Reg := ReadReg; 333 Registers[Reg] := PT(@Memory[SP])^; 334 SP := SP + SizeOf(T); 316 335 end; 317 336 318 337 procedure TCPU.OpcodeCall; 319 338 var 320 Reg: T ;321 begin 322 SP := SP - 1;323 Reg := Read Next;324 Memory[SP]:= IP;339 Reg: TRegIndex; 340 begin 341 SP := SP - SizeOf(T); 342 Reg := ReadReg; 343 PT(@Memory[SP])^ := IP; 325 344 IP := Registers[Reg]; 326 345 end; … … 328 347 procedure TCPU.OpcodeReturn; 329 348 begin 330 IP := Memory[SP];331 SP := SP + 1;349 IP := PT(@Memory[SP])^; 350 SP := SP + SizeOf(T); 332 351 end; 333 352 334 353 procedure TCPU.OpcodeInput; 335 354 var 336 Src, Dest: T ;337 begin 338 Dest := Read Next;339 Src := Read Next;355 Src, Dest: TRegIndex; 356 begin 357 Dest := ReadReg; 358 Src := ReadReg; 340 359 if Assigned(FOnInput) then 341 360 Registers[Dest] := FOnInput(Registers[Src]); … … 344 363 procedure TCPU.OpcodeOutput; 345 364 var 346 Dest, Src: T ;347 begin 348 Dest := Read Next;349 Src := Read Next;365 Dest, Src: TRegIndex; 366 begin 367 Dest := ReadReg; 368 Src := ReadReg; 350 369 if Assigned(FOnOutput) then 351 370 FOnOutput(Registers[Dest], Registers[Src]); … … 354 373 procedure TCPU.OpcodeTestZero; 355 374 var 356 Reg: T ;357 begin 358 Reg := Read Next;375 Reg: TRegIndex; 376 begin 377 Reg := ReadReg; 359 378 Condition := Registers[Reg] = 0; 360 379 end; … … 362 381 procedure TCPU.OpcodeTestNotZero; 363 382 var 364 Reg: T ;365 begin 366 Reg := Read Next;383 Reg: TRegIndex; 384 begin 385 Reg := ReadReg; 367 386 Condition := Registers[Reg] <> 0; 368 387 end; … … 370 389 procedure TCPU.OpcodeExchange; 371 390 var 372 Dest, Src, Temp: T; 373 begin 374 Dest := ReadNext; 375 Src := ReadNext; 391 Dest, Src: TRegIndex; 392 Temp: T; 393 begin 394 Dest := ReadReg; 395 Src := ReadReg; 376 396 Temp := Registers[Dest]; 377 397 Registers[Dest] := Registers[Src]; … … 385 405 Handler: TOpcodeHandler; 386 406 begin 387 Opcode := TOpcode(Read Next);407 Opcode := TOpcode(ReadOpcode); 388 408 if Opcode <= High(TOpcode) then begin 389 409 Handler := OpcodeHandlers[Opcode]; … … 400 420 procedure TCPU.InitOpcodes; 401 421 begin 402 AddOpcode(opNop, @OpcodeNo p);422 AddOpcode(opNop, @OpcodeNoOperation); 403 423 AddOpcode(opHalt, @OpcodeHalt); 404 424 AddOpcode(opAnd, @OpcodeAnd);
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