source: branches/virtualcpu3/UMachine.pas

unit UMachine;


{$DEFINE EXT_IO}
{$DEFINE EXT_ADDRESSING_MODES}
{$DEFINE EXT_ARITHMETIC}
{$DEFINE EXT_LOGICAL}
{$DEFINE EXT_STACK}
{$DEFINE EXT_SUBROUTINE}
{$DEFINE EXT_SHIFT}
{$DEFINE EXT_BLOCK}
{$DEFINE EXT_GENERAL}
{$DEFINE EXT_BIT}
//{$DEFINE EXT_LOWER_WIDTH}

// Extension dependencies
{$IFDEF EXT_SUBROUTINE}
{$DEFINE EXT_STACK}
{$ENDIF}

{$mode objfpc}{$H+}

interface

uses
  Classes, SysUtils;

type
  TOpcode = (opNop, opHalt, opLD, opLDC, opLDM, opSTM, opInc, opDec, opJP, opJr,
    opPush, opPop, opCall, opRet, opAdd, opSub, opMul, opDiv, opShr, opShl,
    opIn, opOut, opXchg, opXor, opOr, opAnd, opJpc, opJrc,
    opTstZ, opTstNZ, opTstC, opTstNC, opLDMD, opSTMD, opLdir, opLddr,
    opBitSet, opBitRes, opBitGet, opBitPut,
    opPrefix8, opPrefix16, opPrefix32, opPrefix64, opPrefix128);

  TOpcodeHandler = procedure of object;

  TDataWidth = (dwNative, dw8, dw16, dw32, dw64, dw128);

  // Goals: Simple to implement, fast execution
  // Address and data have same bit width
  // Memory access with lower bit width?
  // Related instructions grouped as extensions

  { TCPU }

  generic TCPU<T> = class
  type
    TOutputEvent = procedure (Port: T; Value: T) of object;
    TInputEvent = function (Port: T): T of object;
    PT = ^T;
    TOpcodeIndex = Byte;
    POpcodeIndex = ^TOpcodeIndex;
    TRegIndex = Byte;
    PRegIndex = ^TRegIndex;
  var
    Terminated: Boolean;
    OpcodeHandlers: array[TOpcode] of TOpcodeHandler;
    function ReadNext: T;
    {$IFDEF EXT_LOWER_WIDTH}
    function ReadNext8: ShortInt;
    function ReadNext16: SmallInt;
    function ReadNext32: Integer;
    function ReadNext64: Int64;
    {$ENDIF}
    function ReadOpcode: TOpcodeIndex;
    function ReadReg: TRegIndex;
    procedure Step;
    procedure AddOpcode(Opcode: TOpcode; Handler: TOpcodeHandler);
    procedure InitOpcodes;
  private
    FOnInput: TInputEvent;
    FOnOutput: TOutputEvent;
    Condition: Boolean;
    procedure OpcodeNoOperation;
    procedure OpcodeHalt;
    procedure OpcodeIncrement;
    procedure OpcodeDecrement;
    procedure OpcodeJump;
    procedure OpcodeJumpConditional;
    procedure OpcodeJumpRelative;
    procedure OpcodeJumpRelativeConditional;
    procedure OpcodeLoad;
    procedure OpcodeLoadConst;
    procedure OpcodeLoadMemory;
    procedure OpcodeStoreMemory;
    procedure OpcodeTestNotZero;
    procedure OpcodeTestZero;
    procedure OpcodeTestNotCarry;
    procedure OpcodeTestCarry;
    {$IFDEF EXT_LOWER_WIDTH}
    procedure OpcodePrefix8;
    procedure OpcodePrefix16;
    procedure OpcodePrefix32;
    procedure OpcodePrefix64;
    {$ENDIF}
    {$IFDEF EXT_GENERAL}
    procedure OpcodeExchange;
    {$ENDIF}
    {$IFDEF EXT_IO}
    procedure OpcodeInput;
    procedure OpcodeOutput;
    {$ENDIF}
    {$IFDEF EXT_ADDRESSING_MODES}
    procedure OpcodeLoadMemoryDisplacement;
    procedure OpcodeStoreMemoryDisplacement;
    {$ENDIF}
    {$IFDEF EXT_ARITHMETIC}
    procedure OpcodeAddition;
    procedure OpcodeSubtraction;
    procedure OpcodeDivision;
    procedure OpcodeMultiplication;
    {$ENDIF}
    {$IFDEF EXT_LOGICAL}
    procedure OpcodeAnd;
    procedure OpcodeOr;
    procedure OpcodeXor;
    {$ENDIF}
    {$IFDEF EXT_STACK}
    procedure OpcodePop;
    procedure OpcodePush;
    {$ENDIF}
    {$IFDEF EXT_SUBROUTINE}
    procedure OpcodeCall;
    procedure OpcodeReturn;
    {$ENDIF}
    {$IFDEF EXT_SHIFT}
    procedure OpcodeShiftLeft;
    procedure OpcodeShiftRight;
    {$ENDIF}
    {$IFDEF EXT_BLOCK}
    procedure OpcodeLdir;
    procedure OpcodeLddr;
    {$ENDIF}
    {$IFDEF EXT_BIT}
    procedure OpcodeBitSet;
    procedure OpcodeBitReset;
    procedure OpcodeBitGet;
    procedure OpcodeBitPut;
    {$ENDIF}
  public
    Registers: array of T;
    Memory: array of Byte;
    IP: T;
    DataWidth: TDataWidth;
    {$IFDEF EXT_STACK}
    SP: T;
    {$ENDIF}
    procedure Run;
    constructor Create;
    property OnInput: TInputEvent read FOnInput write FOnInput;
    property OnOutput: TOutputEvent read FOnOutput write FOnOutput;
  end;

  { TInstructionWriter }

  generic TInstructionWriter<T> = class
  type
    PT = ^T;
    TOpcodeIndex = Byte;
    POpcodeIndex = ^TOpcodeIndex;
    TRegIndex = Byte;
    PRegIndex = ^TRegIndex;
  var
    Addr: Integer;
    Machine: specialize TCPU<T>;
    procedure AddLoadConst(Reg: TRegIndex; Value: T);
    {$IFDEF EXT_LOWER_WIDTH}
    procedure AddLoadConst8(Reg: TRegIndex; Value: ShortInt);
    procedure AddLoadConst16(Reg: TRegIndex; Value: SmallInt);
    procedure AddLoadConst32(Reg: TRegIndex; Value: Integer);
    procedure AddLoadConst64(Reg: TRegIndex; Value: Int64);
    {$ENDIF}
    procedure AddNop;
    procedure AddHalt;
    procedure AddReg(Reg: TRegIndex);
    procedure AddOpcode(Opcode: TOpcode);
    procedure AddData(Value: T);
    {$IFDEF EXT_LOWER_WIDTH}
    procedure AddData8(Value: ShortInt);
    procedure AddData16(Value: SmallInt);
    procedure AddData32(Value: Integer);
    procedure AddData64(Value: Int64);
    {$ENDIF}
  end;


implementation

{ TInstructionWriter }

procedure TInstructionWriter.AddLoadConst(Reg: TRegIndex; Value: T);
begin
  AddOpcode(opLDC);
  AddReg(Reg);
  AddData(Value);
end;

{$IFDEF EXT_LOWER_WIDTH}
procedure TInstructionWriter.AddLoadConst8(Reg: TRegIndex; Value: ShortInt);
begin
  AddOpcode(opPrefix8);
  AddOpcode(opLDC);
  AddData8(Reg);
  AddData8(Value);
end;

procedure TInstructionWriter.AddLoadConst16(Reg: TRegIndex; Value: SmallInt);
begin
  AddOpcode(opPrefix16);
  AddOpcode(opLDC);
  AddReg(Reg);
  AddData16(Value);
end;

procedure TInstructionWriter.AddLoadConst32(Reg: TRegIndex; Value: Integer);
begin
  AddOpcode(opPrefix32);
  AddOpcode(opLDC);
  AddReg(Reg);
  AddData32(Value);
end;

procedure TInstructionWriter.AddLoadConst64(Reg: TRegIndex; Value: Int64);
begin
  AddOpcode(opPrefix64);
  AddOpcode(opLDC);
  AddReg(Reg);
  AddData64(Value);
end;
{$ENDIF}

procedure TInstructionWriter.AddNop;
begin
  AddOpcode(opNop);
end;

procedure TInstructionWriter.AddHalt;
begin
  AddOpcode(opHalt);
end;

procedure TInstructionWriter.AddReg(Reg: TRegIndex);
begin
  PRegIndex(@(Machine.Memory[Addr]))^ := Reg;
  Inc(Addr, SizeOf(TRegIndex));
end;

procedure TInstructionWriter.AddOpcode(Opcode: TOpcode);
begin
  POpcodeIndex(@(Machine.Memory[Addr]))^ := TOpcodeIndex(Opcode);
  Inc(Addr, SizeOf(TOpcodeIndex));
end;

procedure TInstructionWriter.AddData(Value: T);
begin
  PT(@(Machine.Memory[Addr]))^ := Value;
  Inc(Addr, SizeOf(T));
end;

{$IFDEF EXT_LOWER_WIDTH}
procedure TInstructionWriter.AddData8(Value: ShortInt);
begin
  PShortInt(@(Machine.Memory[Addr]))^ := Value;
  Inc(Addr, SizeOf(ShortInt));
end;

procedure TInstructionWriter.AddData16(Value: SmallInt);
begin
  PSmallInt(@(Machine.Memory[Addr]))^ := Value;
  Inc(Addr, SizeOf(SmallInt));
end;

procedure TInstructionWriter.AddData32(Value: Integer);
begin
  PInteger(@(Machine.Memory[Addr]))^ := Value;
  Inc(Addr, SizeOf(Integer));
end;

procedure TInstructionWriter.AddData64(Value: Int64);
begin
  PInt64(@(Machine.Memory[Addr]))^ := Value;
  Inc(Addr, SizeOf(Int64));
end;
{$ENDIF}

{ TCPU }

function TCPU.ReadNext: T;
begin
  Result := PT(@Memory[IP])^;
  Inc(IP, SizeOf(T));
end;

{$IFDEF EXT_LOWER_WIDTH}
function TCPU.ReadNext8: ShortInt;
begin
  Result := PShortInt(@Memory[IP])^;
  Inc(IP, SizeOf(ShortInt));
end;

function TCPU.ReadNext16: SmallInt;
begin
  Result := PSmallInt(@Memory[IP])^;
  Inc(IP, SizeOf(SmallInt));
end;

function TCPU.ReadNext32: Integer;
begin
  Result := PInteger(@Memory[IP])^;
  Inc(IP, SizeOf(Integer));
end;

function TCPU.ReadNext64: Int64;
begin
  Result := PInt64(@Memory[IP])^;
  Inc(IP, SizeOf(Int64));
end;
{$ENDIF}

function TCPU.ReadOpcode: TOpcodeIndex;
begin
  Result := POpcodeIndex(@Memory[IP])^;
  Inc(IP, SizeOf(TOpcodeIndex));
end;

function TCPU.ReadReg: TRegIndex;
begin
  Result := PRegIndex(@Memory[IP])^;
  Inc(IP, SizeOf(TRegIndex));
end;

procedure TCPU.Run;
begin
  IP := 0;
  {$IFDEF EXT_STACK}
  SP := Length(Memory);
  {$ENDIF}
  {$IFDEF EXT_LOWER_WIDTH}
  DataWidth := dwNative;
  {$ENDIF}
  Terminated := False;
  while not Terminated do
    Step;
end;

constructor TCPU.Create;
begin
  SetLength(Registers, 32);
  SetLength(Memory, 100);
  InitOpcodes;
end;

procedure TCPU.OpcodeNoOperation;
begin
end;

procedure TCPU.OpcodeHalt;
begin
  Terminated := True;
end;

procedure TCPU.OpcodeLoad;
var
  Src, Dest: TRegIndex;
begin
  Dest := ReadReg;
  Src := ReadReg;
  Registers[Dest] := Registers[Src];
end;

procedure TCPU.OpcodeLoadConst;
var
  Reg: TRegIndex;
begin
  Reg := ReadReg;
  {$IFDEF EXT_LOWER_WIDTH}
  case DataWidth of
    dwNative: Registers[Reg] := ReadNext;
    dw8: Registers[Reg] := ReadNext8;
    dw16: Registers[Reg] := ReadNext16;
    dw32: Registers[Reg] := ReadNext32;
    dw64: Registers[Reg] := ReadNext64;
  end;
  {$ELSE}
  Registers[Reg] := ReadNext;
  {$ENDIF}
end;

procedure TCPU.OpcodeLoadMemory;
var
  Src, Dest: TRegIndex;
begin
  Dest := ReadReg;
  Src := ReadReg;
  {$IFDEF EXT_LOWER_WIDTH}
  case DataWidth of
    dwNative: Registers[Dest] := PT(@Memory[Registers[Src]])^;
    dw8: Registers[Dest] := PShortInt(@Memory[Registers[Src]])^;
    dw16: Registers[Dest] := PSmallInt(@Memory[Registers[Src]])^;
    dw32: Registers[Dest] := PInteger(@Memory[Registers[Src]])^;
    dw64: Registers[Dest] := PInt64(@Memory[Registers[Src]])^;
  end;
  {$ELSE}
  Registers[Dest] := PT(@Memory[Registers[Src]])^;
  {$ENDIF}
end;

procedure TCPU.OpcodeStoreMemory;
var
  Src, Dest: TRegIndex;
begin
  Dest := ReadReg;
  Src := ReadReg;
  {$IFDEF EXT_LOWER_WIDTH}
  case DataWidth of
    dwNative: PT(@Memory[Registers[Dest]])^ := Registers[Src];
    dw8: PShortInt(@Memory[Registers[Dest]])^ := Registers[Src];
    dw16: PSmallInt(@Memory[Registers[Dest]])^ := Registers[Src];
    dw32: PInteger(@Memory[Registers[Dest]])^ := Registers[Src];
    dw64: PInt64(@Memory[Registers[Dest]])^ := Registers[Src];
  end;
  {$ELSE}
  PT(@Memory[Registers[Dest]])^ := Registers[Src];
  {$ENDIF}
end;

{$IFDEF EXT_ADDRESSING_MODES}
procedure TCPU.OpcodeLoadMemoryDisplacement;
var
  Disp, Src, Dest: TRegIndex;
begin
  Dest := ReadReg;
  Src := ReadReg;
  Disp := ReadReg;
  Registers[Dest] := PT(@Memory[Registers[Src] + Registers[Disp]])^;
end;

procedure TCPU.OpcodeStoreMemoryDisplacement;
var
  Disp, Src, Dest: TRegIndex;
begin
  Dest := ReadReg;
  Disp := ReadReg;
  Src := ReadReg;
  PT(@Memory[Registers[Dest] + Registers[Disp]])^ := Registers[Src];
end;
{$ENDIF}

procedure TCPU.OpcodeIncrement;
var
  Reg: TRegIndex;
begin
  Reg := ReadReg;
  Registers[Reg] := Registers[Reg] + 1;
end;

procedure TCPU.OpcodeDecrement;
var
  Reg: TRegIndex;
begin
  Reg := ReadReg;
  Registers[Reg] := Registers[Reg] - 1;
end;

{$IFDEF EXT_ARITHMETIC}
procedure TCPU.OpcodeAddition;
var
  Dest, Src: TRegIndex;
begin
  Dest := ReadReg;
  Src := ReadReg;
  Registers[Dest] := Registers[Dest] + Registers[Src];
end;

procedure TCPU.OpcodeSubtraction;
var
  Dest, Src: TRegIndex;
begin
  Dest := ReadReg;
  Src := ReadReg;
  Registers[Dest] := Registers[Dest] - Registers[Src];
end;

procedure TCPU.OpcodeMultiplication;
var
  Dest, Src: TRegIndex;
begin
  Dest := ReadReg;
  Src := ReadReg;
  Registers[Dest] := Registers[Dest] * Registers[Src];
end;

procedure TCPU.OpcodeDivision;
var
  Dest, Src: TRegIndex;
begin
  Dest := ReadReg;
  Src := ReadReg;
  Registers[Dest] := Registers[Dest] div Registers[Src];
end;
{$ENDIF}

{$IFDEF EXT_SHIFT}
procedure TCPU.OpcodeShiftLeft;
var
  Dest, Src: TRegIndex;
begin
  Dest := ReadReg;
  Src := ReadReg;
  Registers[Dest] := Registers[Dest] shl Registers[Src];
end;

procedure TCPU.OpcodeShiftRight;
var
  Src, Dest: TRegIndex;
begin
  Dest := ReadReg;
  Src := ReadReg;
  Registers[Dest] := Registers[Dest] shr Registers[Src];
end;
{$ENDIF}

{$IFDEF EXT_LOGICAL}
procedure TCPU.OpcodeAnd;
var
  Src, Dest: TRegIndex;
begin
  Dest := ReadReg;
  Src := ReadReg;
  Registers[Dest] := Registers[Dest] and Registers[Src];
end;

procedure TCPU.OpcodeOr;
var
  Src, Dest: TRegIndex;
begin
  Dest := ReadReg;
  Src := ReadReg;
  Registers[Dest] := Registers[Dest] or Registers[Src];
end;

procedure TCPU.OpcodeXor;
var
  Src, Dest: TRegIndex;
begin
  Dest := ReadReg;
  Src := ReadReg;
  Registers[Dest] := Registers[Dest] xor Registers[Src];
end;
{$ENDIF}

procedure TCPU.OpcodeJump;
var
  Reg: TRegIndex;
begin
  Reg := ReadReg;
  IP := Registers[Reg];
end;

procedure TCPU.OpcodeJumpConditional;
var
  Reg: TRegIndex;
begin
  Reg := ReadReg;
  if Condition then
    IP := Registers[Reg];
end;

procedure TCPU.OpcodeJumpRelative;
var
  Reg: TRegIndex;
begin
  Reg := ReadReg;
  IP := IP + Registers[Reg];
end;

procedure TCPU.OpcodeJumpRelativeConditional;
var
  Reg: TRegIndex;
begin
  Reg := ReadReg;
  if Condition then
    IP := IP + Registers[Reg];
end;

{$IFDEF EXT_STACK}
procedure TCPU.OpcodePush;
var
  Reg: TRegIndex;
begin
  SP := SP - SizeOf(T);
  Reg := ReadReg;
  PT(@Memory[SP])^ := Registers[Reg];
end;

procedure TCPU.OpcodePop;
var
  Reg: TRegIndex;
begin
  Reg := ReadReg;
  Registers[Reg] := PT(@Memory[SP])^;
  SP := SP + SizeOf(T);
end;
{$ENDIF}

{$IFDEF EXT_SUBROUTINE}
procedure TCPU.OpcodeCall;
var
  Reg: TRegIndex;
begin
  SP := SP - SizeOf(T);
  Reg := ReadReg;
  PT(@Memory[SP])^ := IP;
  IP := Registers[Reg];
end;

procedure TCPU.OpcodeReturn;
begin
  IP := PT(@Memory[SP])^;
  SP := SP + SizeOf(T);
end;
{$ENDIF}

{$IFDEF EXT_IO}
procedure TCPU.OpcodeInput;
var
  Src, Dest: TRegIndex;
begin
  Dest := ReadReg;
  Src := ReadReg;
  if Assigned(FOnInput) then
    Registers[Dest] := FOnInput(Registers[Src]);
end;

procedure TCPU.OpcodeOutput;
var
  Dest, Src: TRegIndex;
begin
  Dest := ReadReg;
  Src := ReadReg;
  if Assigned(FOnOutput) then
    FOnOutput(Registers[Dest], Registers[Src]);
end;
{$ENDIF}

procedure TCPU.OpcodeTestZero;
var
  Reg: TRegIndex;
begin
  Reg := ReadReg;
  Condition := Registers[Reg] = 0;
end;

procedure TCPU.OpcodeTestNotCarry;
var
  Reg1: TRegIndex;
  Reg2: TRegIndex;
begin
  Reg1 := ReadReg;
  Reg2 := ReadReg;
  Condition := Registers[Reg2] <= Registers[Reg1];
end;

procedure TCPU.OpcodeTestCarry;
var
  Reg1: TRegIndex;
  Reg2: TRegIndex;
begin
  Reg1 := ReadReg;
  Reg2 := ReadReg;
  Condition := Registers[Reg2] > Registers[Reg1];
end;

{$IFDEF EXT_LOWER_WIDTH}
procedure TCPU.OpcodePrefix8;
begin
  DataWidth := dw8;
end;

procedure TCPU.OpcodePrefix16;
begin
  DataWidth := dw16;
end;

procedure TCPU.OpcodePrefix32;
begin
  DataWidth := dw32;
end;

procedure TCPU.OpcodePrefix64;
begin
  DataWidth := dw64;
end;
{$ENDIF}

procedure TCPU.OpcodeTestNotZero;
var
  Reg: TRegIndex;
begin
  Reg := ReadReg;
  Condition := Registers[Reg] <> 0;
end;

{$IFDEF EXT_GENERAL}
procedure TCPU.OpcodeExchange;
var
  Dest, Src: TRegIndex;
  Temp: T;
begin
  Dest := ReadReg;
  Src := ReadReg;
  Temp := Registers[Dest];
  Registers[Dest] := Registers[Src];
  Registers[Src] := Temp;
end;
{$ENDIF}

{$IFDEF EXT_BLOCK}
procedure TCPU.OpcodeLdir;
var
  Dest, Src, Count: TRegIndex;
begin
  Dest := ReadReg;
  Src := ReadReg;
  Count := ReadReg;
  while Count > 0 do begin
    Memory[Registers[Dest]] := Memory[Registers[Src]];
    Inc(Registers[Dest]);
    Inc(Registers[Src]);
    Dec(Registers[Count]);
  end;
end;

procedure TCPU.OpcodeLddr;
var
  Dest, Src, Count: TRegIndex;
begin
  Dest := ReadReg;
  Src := ReadReg;
  Count := ReadReg;
  while Count > 0 do begin
    Memory[Registers[Dest]] := Memory[Registers[Src]];
    Dec(Registers[Dest]);
    Dec(Registers[Src]);
    Dec(Registers[Count]);
  end;
end;
{$ENDIF}

{$IFDEF EXT_BIT}
procedure TCPU.OpcodeBitSet;
var
  Reg: TRegIndex;
  Bit: TRegIndex;
begin
  Reg := ReadReg;
  Bit := ReadReg;
  Registers[Reg] := Registers[Reg] or (1 shl Registers[Bit]);
end;

procedure TCPU.OpcodeBitReset;
var
  Reg: TRegIndex;
  Bit: TRegIndex;
begin
  Reg := ReadReg;
  Bit := ReadReg;
  Registers[Reg] := Registers[Reg] and ((1 shl Registers[Bit]) xor -1);
end;

procedure TCPU.OpcodeBitGet;
var
  Reg: TRegIndex;
  Bit: TRegIndex;
begin
  Reg := ReadReg;
  Bit := ReadReg;
  Condition := ((Registers[Reg] shr Registers[Bit]) and 1) = 1;
end;

procedure TCPU.OpcodeBitPut;
var
  Reg: TRegIndex;
  Bit: TRegIndex;
begin
  Reg := ReadReg;
  Bit := ReadReg;
  if Condition then
    Registers[Reg] := Registers[Reg] or (1 shl Registers[Bit]);
end;
{$ENDIF}

procedure TCPU.Step;
var
  Opcode: TOpcode;
  Handler: TOpcodeHandler;
begin
  Opcode := TOpcode(ReadOpcode);
  if Opcode <= High(TOpcode) then begin
    Handler := OpcodeHandlers[Opcode];
    if Assigned(Handler) then Handler
    else raise Exception.Create('Missing handler for opcode + ' + IntToStr(Integer(Opcode)));
  end else raise Exception.Create('Unknown opcode: ' + IntToStr(Integer(Opcode)));
  {$IFDEF EXT_LOWER_WIDTH}
  if (Opcode <> opPrefix8) and (Opcode <> opPrefix16) and (Opcode <> opPrefix32) and
  (Opcode <> opPrefix64) then
    DataWidth := dwNative;
  {$ENDIF}
end;

procedure TCPU.AddOpcode(Opcode: TOpcode; Handler: TOpcodeHandler);
begin
  OpcodeHandlers[Opcode] := Handler;
end;

procedure TCPU.InitOpcodes;
begin
  AddOpcode(opNop, @OpcodeNoOperation);
  AddOpcode(opHalt, @OpcodeHalt);
  AddOpcode(opLD, @OpcodeLoad);
  AddOpcode(opLDC, @OpcodeLoadConst);
  AddOpcode(opLDM, @OpcodeLoadMemory);
  AddOpcode(opSTM, @OpcodeStoreMemory);
  AddOpcode(opInc, @OpcodeIncrement);
  AddOpcode(opDec, @OpcodeDecrement);
  AddOpcode(opTstNZ, @OpcodeTestNotZero);
  AddOpcode(opTstZ, @OpcodeTestZero);
  AddOpcode(opTstNC, @OpcodeTestNotCarry);
  AddOpcode(opTstC, @OpcodeTestCarry);
  AddOpcode(opJP, @OpcodeJump);
  AddOpcode(opJpc, @OpcodeJumpConditional);
  AddOpcode(opJR, @OpcodeJumpRelative);
  AddOpcode(opJRC, @OpcodeJumpRelativeConditional);
  {$IFDEF EXT_BIT}
  AddOpcode(opBitSet, @OpcodeBitSet);
  AddOpcode(opBitRes, @OpcodeBitReset);
  AddOpcode(opBitPut, @OpcodeBitPut);
  AddOpcode(opBitGet, @OpcodeBitGet);
  {$ENDIF}
  {$IFDEF EXT_LOGICAL}
  AddOpcode(opAnd, @OpcodeAnd);
  AddOpcode(opOr, @OpcodeOr);
  AddOpcode(opXor, @OpcodeXor);
  {$ENDIF}
  {$IFDEF EXT_ADDRESSING_MODES}
  AddOpcode(opLDMD, @OpcodeLoadMemoryDisplacement);
  AddOpcode(opSTMD, @OpcodeStoreMemoryDisplacement);
  {$ENDIF}
  {$IFDEF EXT_SUBROUTINE}
  AddOpcode(opCall, @OpcodeCall);
  AddOpcode(opRet, @OpcodeReturn);
  {$ENDIF}
  {$IFDEF EXT_STACK}
  AddOpcode(opPush, @OpcodePush);
  AddOpcode(opPop, @OpcodePop);
  {$ENDIF}
  {$IFDEF EXT_ARITHMETIC}
  AddOpcode(opAdd, @OpcodeAddition);
  AddOpcode(opSub, @OpcodeSubtraction);
  AddOpcode(opMul, @OpcodeMultiplication);
  AddOpcode(opDiv, @OpcodeDivision);
  {$ENDIF}
  {$IFDEF EXT_GENERAL}
  AddOpcode(opXchg, @OpcodeExchange);
  {$ENDIF}
  {$IFDEF EXT_SHIFT}
  AddOpcode(opShl, @OpcodeShiftLeft);
  AddOpcode(opShr, @OpcodeShiftRight);
  {$ENDIF}
  {$IFDEF EXT_IO}
  AddOpcode(opIn, @OpcodeInput);
  AddOpcode(opOut, @OpcodeOutput);
  {$ENDIF}
  {$IFDEF EXT_BLOCK}
  AddOpcode(opLdir, @OpcodeLdir);
  AddOpcode(opLddr, @OpcodeLddr);
  {$ENDIF}
end;

end.