Ignore:
Timestamp:
Nov 25, 2023, 11:47:52 PM (5 months ago)
Author:
chronos
Message:
  • Fixed: Assembler and disassembler to work correctly with supported instructions.
File:
1 edited

Legend:

Unmodified
Added
Removed
  • branches/ByteArray/Cpu.pas

    r57 r59  
    1212    inLoadMem, inLoadMemSize,
    1313    inStoreMem, inStoreMemSize,
     14    inLoadMemIndex, inLoadMemIndexSize,
     15    inStoreMemIndex, inStoreMemIndexSize,
    1416    inInput, inInputSize,
    1517    inOutput, inOutputSize,
     
    3840    inCompare);
    3941
    40   TRegIndex = (riA, riB, riC, riD, riE, riF, riG, riH);
     42  TRegIndex = Byte;
    4143
    4244  TInstructionEvent = procedure of object;
     
    6466    procedure InstructionStoreMem;
    6567    procedure InstructionStoreMemSize;
     68    procedure InstructionLoadMemIndex;
     69    procedure InstructionLoadMemIndexSize;
     70    procedure InstructionStoreMemIndex;
     71    procedure InstructionStoreMemIndexSize;
    6672    procedure InstructionJump;
    6773    procedure InstructionJumpSize;
     
    213219procedure TCpu.InstructionLoadMem;
    214220var
    215   Address: TBigInt;
    216   RegIndex: TRegIndex;
    217 begin
    218   RegIndex := ReadRegIndex;
    219   Address := Read(AddressWidth);
    220   Regs[RegIndex] := Memory.Read(Address, DataWidth);
     221  RegIndex1: TRegIndex;
     222  RegIndex2: TRegIndex;
     223begin
     224  RegIndex1 := ReadRegIndex;
     225  RegIndex2 := ReadRegIndex;
     226  Regs[RegIndex1] := Memory.Read(Regs[RegIndex2], DataWidth);
    221227end;
    222228
     
    224230var
    225231  DataSize: TBigIntSize;
    226   AddressSize: TBigIntSize;
    227   Address: TBigInt;
    228   RegIndex: TRegIndex;
    229 begin
    230   DataSize := ReadSize;
    231   AddressSize := Read(SizeOf(TBigIntSize));
    232   RegIndex := ReadRegIndex;
    233   Address := Read(AddressSize);
    234   Regs[RegIndex] := Memory.Read(Address, DataSize);
     232  RegIndex1: TRegIndex;
     233  RegIndex2: TRegIndex;
     234begin
     235  DataSize := ReadSize;
     236  RegIndex1 := ReadRegIndex;
     237  RegIndex2 := ReadRegIndex;
     238  Regs[RegIndex1] := Memory.Read(Regs[RegIndex2], DataSize);
    235239end;
    236240
    237241procedure TCpu.InstructionStoreMem;
    238242var
    239   Address: TBigInt;
    240   RegIndex: TRegIndex;
    241 begin
    242   Address := Read(AddressWidth);
    243   RegIndex := ReadRegIndex;
    244   Memory.Write(Address, DataWidth, Regs[RegIndex]);
     243  RegIndex1: TRegIndex;
     244  RegIndex2: TRegIndex;
     245begin
     246  RegIndex1 := ReadRegIndex;
     247  RegIndex2 := ReadRegIndex;
     248  Memory.Write(Regs[RegIndex1], DataWidth, Regs[RegIndex2]);
    245249end;
    246250
     
    248252var
    249253  DataSize: TBigIntSize;
    250   AddressSize: TBigIntSize;
    251   Address: TBigInt;
    252   RegIndex: TRegIndex;
    253 begin
    254   DataSize := ReadSize;
    255   AddressSize := Read(SizeOf(TBigIntSize));
    256   Address := Read(AddressSize);
    257   RegIndex := ReadRegIndex;
    258   Memory.Write(Address, DataSize, Regs[RegIndex]);
     254  RegIndex1: TRegIndex;
     255  RegIndex2: TRegIndex;
     256begin
     257  DataSize := ReadSize;
     258  RegIndex1 := ReadRegIndex;
     259  RegIndex2 := ReadRegIndex;
     260  Memory.Write(Regs[RegIndex1], DataSize, Regs[RegIndex2]);
     261end;
     262
     263procedure TCpu.InstructionLoadMemIndex;
     264var
     265  RegIndex1: TRegIndex;
     266  RegIndex2: TRegIndex;
     267  RelativeAddress: TBigInt;
     268begin
     269  RegIndex1 := ReadRegIndex;
     270  RegIndex2 := ReadRegIndex;
     271  RelativeAddress := Read(AddressWidth);
     272  Regs[RegIndex1] := Memory.Read(Regs[RegIndex2] + RelativeAddress, DataWidth);
     273end;
     274
     275procedure TCpu.InstructionLoadMemIndexSize;
     276var
     277  DataSize: TBigIntSize;
     278  RegIndex1: TRegIndex;
     279  RegIndex2: TRegIndex;
     280  RelativeAddress: TBigInt;
     281begin
     282  DataSize := ReadSize;
     283  RegIndex1 := ReadRegIndex;
     284  RegIndex2 := ReadRegIndex;
     285  RelativeAddress := Read(AddressWidth);
     286  Regs[RegIndex1] := Memory.Read(Regs[RegIndex2] + RelativeAddress, DataSize);
     287end;
     288
     289procedure TCpu.InstructionStoreMemIndex;
     290var
     291  RegIndex1: TRegIndex;
     292  RegIndex2: TRegIndex;
     293  RelativeAddress: TBigInt;
     294begin
     295  RegIndex1 := ReadRegIndex;
     296  RegIndex2 := ReadRegIndex;
     297  RelativeAddress := Read(AddressWidth);
     298  Memory.Write(Regs[RegIndex1] + RelativeAddress, DataWidth, Regs[RegIndex2]);
     299end;
     300
     301procedure TCpu.InstructionStoreMemIndexSize;
     302var
     303  DataSize: TBigIntSize;
     304  RegIndex1: TRegIndex;
     305  RegIndex2: TRegIndex;
     306  RelativeAddress: TBigInt;
     307begin
     308  DataSize := ReadSize;
     309  RegIndex1 := ReadRegIndex;
     310  RegIndex2 := ReadRegIndex;
     311  RelativeAddress := Read(AddressWidth);
     312  Memory.Write(Regs[RegIndex1] + RelativeAddress, DataSize, Regs[RegIndex2]);
    259313end;
    260314
     
    603657  FInstructions[inStoreMem] := InstructionStoreMem;
    604658  FInstructions[inStoreMemSize] := InstructionStoreMemSize;
     659  FInstructions[inLoadMemIndex] := InstructionLoadMemIndex;
     660  FInstructions[inLoadMemIndexSize] := InstructionLoadMemIndexSize;
     661  FInstructions[inStoreMemIndex] := InstructionStoreMemIndex;
     662  FInstructions[inStoreMemIndexSize] := InstructionStoreMemIndexSize;
    605663  FInstructions[inJump] := InstructionJump;
    606664  FInstructions[inJumpSize] := InstructionJumpSize;
     
    802860- bit index 2048 (256 * 8) (8 + 3) bits = 2^11
    803861
     862LD   R0, R1
     863LD2  R0, R1
     864LD.2 R0, R1
     865LD:2 R0, R1
     866LD   D2, R0, R1
     867LD   D2, A16, R0, (R1)
     868LD   D2:A16: R0, (R1)
     869RET
     870RET2
     871RET.2
     872RET:2
     873RET  A2
     874PUSH   R0
     875PUSH2  R0
     876PUSH.2 R0
     877PUSH:2 R0
     878PUSH   D2, R0
     879PUSH   D2:R0
     880PUSH   R0.2
     881PUSH   R0:2
     882LD     (R0), (R2)
     883LD     D1, A2, (R0), (R2)
     884LDIR   (R0), (R1), R2
     885LDIR   D1, A2, (R0), (R1), R2
     886LDI
     887OUT    (R0), R1
     888OUT    D1, (R0), R1
     889OUT    D1, A2, (R0), R1
    804890
    805891
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