Changeset 34 for branches/UltimatOS/UCpu.pas

Timestamp:

Jul 12, 2022, 11:51:47 PM (22 months ago)

Author:

chronos

Message:

• Modified: Execute instructions as array of instruction handlers.
• Modified: Optimized some methods call with inline directive.

File:

• branches/UltimatOS/UCpu.pas (modified) (5 diffs)

branches/UltimatOS/UCpu.pas

@@ -21 +21 @@
 
   TCpu = class;
+  TInstructionHandler = procedure of object;
 
   { TCpuThread }
@@ -40 +41 @@
     InterruptVector: Integer;
     InterruptEnabled: Boolean;
+    FInstructionHandlers: array[TInstruction] of TInstructionHandler;
     function GetRunning: Boolean;
-    function ReadByte: Byte;
-    function ReadAddress: TAddress;
-    function ReadData: TData;
-    procedure Push(Value: Integer);
-    function Pop: Integer;
+    function ReadByte: Byte; inline;
+    function ReadAddress: TAddress; inline;
+    function ReadData: TData; inline;
+    procedure Push(Value: Integer); inline;
+    function Pop: Integer; inline;
     procedure SetRunning(AValue: Boolean);
+    procedure InitInstructions;
+    procedure InstructionNop;
+    procedure InstructionHalt;
+    procedure InstructionSet;
+    procedure InstructionInput;
+    procedure InstructionOutput;
+    procedure InstructionInc;
+    procedure InstructionDec;
+    procedure InstructionJp;
+    procedure InstructionJpnz;
+    procedure InstructionJpz;
+    procedure InstructionAdd;
+    procedure InstructionSub;
+    procedure InstructionCall;
+    procedure InstructionRet;
+    procedure InstructionPush;
+    procedure InstructionPop;
+    procedure InstructionCopy;
+    procedure InstructionShl;
+    procedure InstructionShr;
+    procedure InstructionLoad;
+    procedure InstructionLoadi;
+    procedure InstructionStore;
+    procedure InstructionMul;
+    procedure InstructionAnd;
+    procedure InstructionAndi;
+    procedure InstructionOr;
+    procedure InstructionXor;
+    procedure InstructionInt;
+    procedure InstructionReti;
+    procedure InstructionEnableInt;
+    procedure InstructionDisableInt;
   public
     ExecutedCount: Integer;
@@ -135 +169 @@
 end;
 
+procedure TCpu.InitInstructions;
+begin
+  FInstructionHandlers[inNop] := InstructionNop;
+  FInstructionHandlers[inHalt] := InstructionHalt;
+  FInstructionHandlers[inSet] := InstructionSet;
+  FInstructionHandlers[inInput] := InstructionInput;
+  FInstructionHandlers[inOutput] := InstructionOutput;
+  FInstructionHandlers[inInc] := InstructionInc;
+  FInstructionHandlers[inDec] := InstructionDec;
+  FInstructionHandlers[inJp] := InstructionJp;
+  FInstructionHandlers[inJpz] := InstructionJpz;
+  FInstructionHandlers[inJpnz] := InstructionJpnz;
+  FInstructionHandlers[inAdd] := InstructionAdd;
+  FInstructionHandlers[inSub] := InstructionSub;
+  FInstructionHandlers[inCall] := InstructionCall;
+  FInstructionHandlers[inRet] := InstructionRet;
+  FInstructionHandlers[inPush] := InstructionPush;
+  FInstructionHandlers[inPop] := InstructionPop;
+  FInstructionHandlers[inCopy] := InstructionCopy;
+  FInstructionHandlers[inShl] := InstructionShl;
+  FInstructionHandlers[inShr] := InstructionShr;
+  FInstructionHandlers[inLoad] := InstructionLoad;
+  FInstructionHandlers[inLoadi] := InstructionLoadi;
+  FInstructionHandlers[inStore] := InstructionStore;
+  FInstructionHandlers[inMul] := InstructionMul;
+  FInstructionHandlers[inAnd] := InstructionAnd;
+  FInstructionHandlers[inAndi] := InstructionAndi;
+  FInstructionHandlers[inOr] := InstructionOr;
+  FInstructionHandlers[inXor] := InstructionXor;
+  FInstructionHandlers[inInt] := InstructionInt;
+  FInstructionHandlers[inReti] := InstructionReti;
+  FInstructionHandlers[inEnableInt] := InstructionEnableInt;
+  FInstructionHandlers[inDisableInt] := InstructionDisableInt;
+end;
+
+procedure TCpu.InstructionNop;
+begin
+  // No operation
+end;
+
+procedure TCpu.InstructionHalt;
+begin
+  Terminated := True;
+end;
+
+procedure TCpu.InstructionSet;
+var
+  RegIndex: Byte;
+begin
+  RegIndex := ReadByte;
+  R[RegIndex] := ReadData;
+end;
+
+procedure TCpu.InstructionInput;
+var
+  RegIndex: Byte;
+  Address: TAddress;
+begin
+  RegIndex := ReadByte;
+  Address := ReadAddress;
+  if Assigned(FOnInput) then R[RegIndex] := FOnInput(Address)
+    else R[RegIndex] := 0;
+end;
+
+procedure TCpu.InstructionOutput;
+var
+  RegIndex: Byte;
+  Address: TAddress;
+begin
+  Address := ReadAddress;
+  RegIndex := ReadByte;
+  if Assigned(FOnOutput) then FOnOutput(Address, R[RegIndex]);
+end;
+
+procedure TCpu.InstructionInc;
+var
+  RegIndex: Byte;
+begin
+  RegIndex := ReadByte;
+  R[RegIndex] := R[RegIndex] + 1;
+end;
+
+procedure TCpu.InstructionDec;
+var
+  RegIndex: Byte;
+begin
+  RegIndex := ReadByte;
+  R[RegIndex] := R[RegIndex] - 1;
+end;
+
+procedure TCpu.InstructionJp;
+begin
+  IP := ReadAddress;
+end;
+
+procedure TCpu.InstructionJpnz;
+var
+  RegIndex: Byte;
+  Address: TAddress;
+begin
+  RegIndex := ReadByte;
+  Address := ReadAddress;
+  if R[RegIndex] <> 0 then IP := Address;
+end;
+
+procedure TCpu.InstructionJpz;
+var
+  RegIndex: Byte;
+  Address: TAddress;
+begin
+  RegIndex := ReadByte;
+  Address := ReadAddress;
+  if R[RegIndex] = 0 then IP := Address;
+end;
+
+procedure TCpu.InstructionAdd;
+var
+  RegIndex: Byte;
+  RegIndex2: Byte;
+begin
+  RegIndex := ReadByte;
+  RegIndex2 := ReadByte;
+  R[RegIndex] := R[RegIndex] + R[RegIndex2];
+end;
+
+procedure TCpu.InstructionSub;
+var
+  RegIndex: Byte;
+  RegIndex2: Byte;
+begin
+  RegIndex := ReadByte;
+  RegIndex2 := ReadByte;
+  R[RegIndex] := R[RegIndex] - R[RegIndex2];
+end;
+
+procedure TCpu.InstructionCall;
+var
+  Address: TAddress;
+begin
+  Address := ReadAddress;
+  Push(IP);
+  IP := Address;
+end;
+
+procedure TCpu.InstructionRet;
+begin
+  IP := Pop;
+end;
+
+procedure TCpu.InstructionPush;
+begin
+  Push(R[ReadByte]);
+end;
+
+procedure TCpu.InstructionPop;
+begin
+  R[ReadByte] := Pop;
+end;
+
+procedure TCpu.InstructionCopy;
+var
+  RegIndex: Byte;
+  RegIndex2: Byte;
+begin
+  RegIndex := ReadByte;
+  RegIndex2 := ReadByte;
+  R[RegIndex] := R[RegIndex2];
+end;
+
+procedure TCpu.InstructionShl;
+var
+  RegIndex: Byte;
+  Num: Byte;
+begin
+  RegIndex := ReadByte;
+  Num := ReadByte;
+  R[RegIndex] := R[RegIndex] shl Num;
+end;
+
+procedure TCpu.InstructionShr;
+var
+  RegIndex: Byte;
+  Num: Byte;
+begin
+  RegIndex := ReadByte;
+  Num := ReadByte;
+  R[RegIndex] := R[RegIndex] shr Num;
+end;
+
+procedure TCpu.InstructionLoad;
+var
+  RegIndex: Byte;
+  RegIndex2: Byte;
+begin
+  RegIndex := ReadByte;
+  RegIndex2 := ReadByte;
+  R[RegIndex] := PData(@Memory.Data[R[RegIndex2]])^;
+end;
+
+procedure TCpu.InstructionLoadi;
+var
+  RegIndex: Byte;
+  Address: TAddress;
+begin
+  RegIndex := ReadByte;
+  Address := ReadAddress;
+  R[RegIndex] := PData(@Memory.Data[Address])^;
+end;
+
+procedure TCpu.InstructionStore;
+var
+  RegIndex: Byte;
+  RegIndex2: Byte;
+begin
+  RegIndex := ReadByte;
+  RegIndex2 := ReadByte;
+  PData(@Memory.Data[R[RegIndex2]])^ := R[RegIndex];
+end;
+
+procedure TCpu.InstructionMul;
+var
+  RegIndex: Byte;
+  RegIndex2: Byte;
+begin
+  RegIndex := ReadByte;
+  RegIndex2 := ReadByte;
+  R[RegIndex] := R[RegIndex] * R[RegIndex2];
+end;
+
+procedure TCpu.InstructionAnd;
+var
+  RegIndex: Byte;
+  RegIndex2: Byte;
+begin
+  RegIndex := ReadByte;
+  RegIndex2 := ReadByte;
+  R[RegIndex] := R[RegIndex] and R[RegIndex2];
+end;
+
+procedure TCpu.InstructionAndi;
+var
+  RegIndex: Byte;
+begin
+  RegIndex := ReadByte;
+  R[RegIndex] := R[RegIndex] and ReadData;
+end;
+
+procedure TCpu.InstructionOr;
+var
+  RegIndex: Byte;
+  RegIndex2: Byte;
+begin
+  RegIndex := ReadByte;
+  RegIndex2 := ReadByte;
+  R[RegIndex] := R[RegIndex] or R[RegIndex2];
+end;
+
+procedure TCpu.InstructionXor;
+var
+  RegIndex: Byte;
+  RegIndex2: Byte;
+begin
+  RegIndex := ReadByte;
+  RegIndex2 := ReadByte;
+  R[RegIndex] := R[RegIndex] xor R[RegIndex2];
+end;
+
+procedure TCpu.InstructionInt;
+begin
+  Interrupt(ReadByte);
+end;
+
+procedure TCpu.InstructionReti;
+begin
+  IP := Pop;
+  InterruptEnabled := True;
+end;
+
+procedure TCpu.InstructionEnableInt;
+begin
+  InterruptEnabled := True;
+end;
+
+procedure TCpu.InstructionDisableInt;
+begin
+  InterruptEnabled := False;
+end;
+
 procedure TCpu.Run;
 begin
@@ -161 +483 @@
 var
   Instruction: TInstruction;
-  Address: Integer;
-  RegIndex: Byte;
-  RegIndex2: Byte;
-  Num: Byte;
 begin
   Instruction := TInstruction(ReadByte);
+  if Assigned(FInstructionHandlers[Instruction]) then
+    FInstructionHandlers[Instruction]
+    else raise Exception.Create('Missing handler for instruction ' + IntToStr(Integer(Instruction)));
   Inc(ExecutedCount);
-  case Instruction of
-    inNop: ;
-    inHalt: Terminated := True;
-    inSet: begin
-      RegIndex := ReadByte;
-      R[RegIndex] := ReadData;
-    end;
-    inLoad: begin
-      RegIndex := ReadByte;
-      RegIndex2 := ReadByte;
-      R[RegIndex] := PData(@Memory.Data[R[RegIndex2]])^;
-    end;
-    inLoadi: begin
-      RegIndex := ReadByte;
-      Address := ReadAddress;
-      R[RegIndex] := PData(@Memory.Data[Address])^;
-    end;
-    inStore: begin
-      RegIndex := ReadByte;
-      RegIndex2 := ReadByte;
-      PData(@Memory.Data[R[RegIndex2]])^ := R[RegIndex];
-    end;
-    inInput: begin
-      RegIndex := ReadByte;
-      Address := ReadAddress;
-      if Assigned(FOnInput) then R[RegIndex] := FOnInput(Address)
-        else R[RegIndex] := 0;
-    end;
-    inOutput: begin
-      Address := ReadAddress;
-      RegIndex := ReadByte;
-      if Assigned(FOnOutput) then FOnOutput(Address, R[RegIndex]);
-    end;
-    inInc: begin
-      RegIndex := ReadByte;
-      R[RegIndex] := R[RegIndex] + 1;
-    end;
-    inDec: begin
-      RegIndex := ReadByte;
-      R[RegIndex] := R[RegIndex] - 1;
-    end;
-    inJp: begin
-      IP := ReadAddress;
-    end;
-    inJpz: begin
-      RegIndex := ReadByte;
-      Address := ReadAddress;
-      if R[RegIndex] = 0 then IP := Address;
-    end;
-    inJpnz: begin
-      RegIndex := ReadByte;
-      Address := ReadAddress;
-      if R[RegIndex] <> 0 then IP := Address;
-    end;
-    inAdd: begin
-      RegIndex := ReadByte;
-      RegIndex2 := ReadByte;
-      R[RegIndex] := R[RegIndex] + R[RegIndex2];
-    end;
-    inSub: begin
-      RegIndex := ReadByte;
-      RegIndex2 := ReadByte;
-      R[RegIndex] := R[RegIndex] - R[RegIndex2];
-    end;
-    inPush: begin
-      RegIndex := ReadByte;
-      Push(R[RegIndex]);
-    end;
-    inPop: begin
-      RegIndex := ReadByte;
-      R[RegIndex] := Pop;
-    end;
-    inCall: begin
-      Address := ReadAddress;
-      Push(IP);
-      IP := Address;
-    end;
-    inRet: begin
-      IP := Pop;
-    end;
-    inCopy: begin
-      RegIndex := ReadByte;
-      RegIndex2 := ReadByte;
-      R[RegIndex] := R[RegIndex2];
-    end;
-    inShl: begin
-      RegIndex := ReadByte;
-      Num := ReadByte;
-      R[RegIndex] := R[RegIndex] shl Num;
-    end;
-    inShr: begin
-      RegIndex := ReadByte;
-      Num := ReadByte;
-      R[RegIndex] := R[RegIndex] shr Num;
-    end;
-    inMul: begin
-      RegIndex := ReadByte;
-      RegIndex2 := ReadByte;
-      R[RegIndex] := R[RegIndex] * R[RegIndex2];
-    end;
-    inAnd: begin
-      RegIndex := ReadByte;
-      RegIndex2 := ReadByte;
-      R[RegIndex] := R[RegIndex] and R[RegIndex2];
-    end;
-    inAndi: begin
-      RegIndex := ReadByte;
-      R[RegIndex] := R[RegIndex] and ReadData;
-    end;
-    inOr: begin
-      RegIndex := ReadByte;
-      RegIndex2 := ReadByte;
-      R[RegIndex] := R[RegIndex] or R[RegIndex2];
-    end;
-    inXor: begin
-      RegIndex := ReadByte;
-      RegIndex2 := ReadByte;
-      R[RegIndex] := R[RegIndex] xor R[RegIndex2];
-    end;
-    inInt: begin
-      Interrupt(ReadByte);
-    end;
-    inReti: begin
-      IP := Pop;
-      InterruptEnabled := True;
-    end;
-    inEnableInt: InterruptEnabled := True;
-    inDisableInt: InterruptEnabled := False;
-  end;
 end;
 
@@ -319 +511 @@
 constructor TCpu.Create;
 begin
+  InitInstructions;
 end;