Changeset 183 for branches/virtualcpu4/UCpu.pas

Timestamp:

Apr 24, 2019, 5:04:53 PM (5 years ago)

Author:

chronos

Message:

• Added: New instruction Convert which can convert numbers between different widths.

Location:

branches/virtualcpu4

Files:

• . (modified) (1 prop)
• UCpu.pas (modified) (6 diffs)

branches/virtualcpu4

@@ -5 +5 @@
 *.res
 heaptrclog.trc
+*.dbg

@@ -5 +5 @@
 *.res
 heaptrclog.trc
+*.dbg

branches/virtualcpu4/UCpu.pas

@@ -15 +15 @@
     opDataPrefix32, opDataPrefix64, opDataSize, opAddrSize, opTest, opAnd, opOr,
     opXor, opLddr, opLdir, opMul, opDiv, opMod, opAddrPrefix8, opAddrPrefix16,
-    opAddrPrefix32, opAddrPrefix64);
+    opAddrPrefix32, opAddrPrefix64, opConvert);
 
   TAddressSigned = Int64;
@@ -51 +51 @@
     Z: Boolean;
     Thread: TCpuThread;
+    procedure InstConvert;
     procedure InstNop;
     procedure InstHalt;
@@ -197 +198 @@
     (Name: 'AP16'; Param1: prNone; Param2: prNone; Param3: prNone; Prefix: True),
     (Name: 'AP32'; Param1: prNone; Param2: prNone; Param3: prNone; Prefix: True),
-    (Name: 'AP64'; Param1: prNone; Param2: prNone; Param3: prNone; Prefix: True)
+    (Name: 'AP64'; Param1: prNone; Param2: prNone; Param3: prNone; Prefix: True),
+    (Name: 'CON'; Param1: prReg; Param2: prNone; Param3: prNone; Prefix: True)
   );
 
@@ -770 +772 @@
   end;
 end;
+
+procedure TCpu.InstConvert;
+var
+  R: TRegIndex;
+begin
+  R := Read8;
+  case AddrSize of
+    bw8: case DataSize of
+      bw8: Registers[R].B := Registers[R].B;
+      bw16: Registers[R].B := Registers[R].W;
+      bw32: Registers[R].B := Registers[R].D;
+      bw64: Registers[R].B := Registers[R].Q;
+    end;
+    bw16: case DataSize of
+      bw8: Registers[R].W := Registers[R].B;
+      bw16: Registers[R].W := Registers[R].W;
+      bw32: Registers[R].W := Registers[R].D;
+      bw64: Registers[R].W := Registers[R].Q;
+    end;
+    bw32: case DataSize of
+      bw8: Registers[R].D := Registers[R].B;
+      bw16: Registers[R].D := Registers[R].W;
+      bw32: Registers[R].D := Registers[R].D;
+      bw64: Registers[R].D := Registers[R].Q;
+    end;
+    bw64: case DataSize of
+      bw8: Registers[R].Q := Registers[R].B;
+      bw16: Registers[R].Q := Registers[R].W;
+      bw32: Registers[R].Q := Registers[R].D;
+      bw64: Registers[R].Q := Registers[R].Q;
+    end;
+  end;
+end;
+
 
 procedure TCpu.InstLddr;
@@ -1088 +1124 @@
   Instructions[opDataPrefix16] := InstDataPrefix16;
   Instructions[opDataPrefix32] := InstDataPrefix32;
-  Instructions[opDataPrefix32] := InstDataPrefix64;
+  Instructions[opDataPrefix64] := InstDataPrefix64;
   Instructions[opAddrSize] := InstAddrSize;
   Instructions[opAddrPrefix8] := InstAddrPrefix8;
   Instructions[opAddrPrefix16] := InstAddrPrefix16;
   Instructions[opAddrPrefix32] := InstAddrPrefix32;
-  Instructions[opAddrPrefix32] := InstAddrPrefix64;
+  Instructions[opAddrPrefix64] := InstAddrPrefix64;
   Instructions[opTest] := InstTest;
   Instructions[opAnd] := InstAnd;
@@ -1103 +1139 @@
   Instructions[opDiv] := InstDiv;
   Instructions[opMod] := InstMod;
+  Instructions[opConvert] := InstConvert;
 end;
 

@@ -5 +5 @@
 *.res
 heaptrclog.trc
+*.dbg