1 | unit Cpu;
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2 |
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3 | interface
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4 |
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5 | uses
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6 | Classes, SysUtils, Int, Channel;
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7 |
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8 | type
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9 | TInstruction = (inNop, inHalt,
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10 | inLoadConst, inLoadConstSize,
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11 | inLoad, inLoadSize,
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12 | inLoadMem, inLoadMemSize,
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13 | inStoreMem, inStoreMemSize,
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14 | inLoadMemIndex, inLoadMemIndexSize,
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15 | inStoreMemIndex, inStoreMemIndexSize,
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16 | inInput, inInputSize,
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17 | inOutput, inOutputSize,
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18 | inInc, inIncSize, inDec, inDecSize,
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19 | inAdd, inAddSize, inSub, inSubSize,
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20 | inShr, inShrSize, inShl, inShlSize,
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21 | inXor, inXorSize, inAnd, inAndSize, inOr, inOrSize,
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22 | inJump, inJumpSize,
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23 | inJumpNotZero, inJumpNotZeroSize,
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24 | inJumpZero, inJumpZeroSize,
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25 | inJumpRel, inJumpRelSize,
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26 | inCall, inCallSize,
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27 | inRet, inRetSize,
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28 | inPush, inPushSize,
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29 | inPop, inPopSize,
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30 | inSet, inSetSize,
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31 | inRes, inResSize,
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32 | inBit, inBitSize,
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33 | inMul, inMulSize,
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34 | inDiv, inDivSize,
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35 | inLdir, inLdi, inLddr, inLdd,
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36 | inInir, inIni, inIndr, inInd,
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37 | inOtir, inOti, inOtdr, inOtd,
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38 | inCpir, inCpi, inCpdr, inCpd,
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39 | inEx, inEnableInterrupts, inDisableInterrupts,
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40 | inCompare);
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41 |
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42 | TRegIndex = Byte;
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43 |
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44 | TInstructionEvent = procedure of object;
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45 | TCpuThread = class;
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46 |
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47 | { TCpu }
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48 |
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49 | TCpu = class
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50 | private
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51 | FHalted: Boolean;
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52 | FRunning: Boolean;
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53 | FThread: TCpuThread;
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54 | FInstructions: array[TInstruction] of TInstructionEvent;
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55 | FTicks: QWord;
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56 | procedure Push(Value: TInt; Size: TIntSize);
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57 | function Pop(Size: TIntSize): TInt;
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58 | procedure InstructionNop;
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59 | procedure InstructionHalt;
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60 | procedure InstructionLoadConst;
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61 | procedure InstructionLoadConstSize;
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62 | procedure InstructionLoad;
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63 | procedure InstructionLoadSize;
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64 | procedure InstructionLoadMem;
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65 | procedure InstructionLoadMemSize;
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66 | procedure InstructionStoreMem;
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67 | procedure InstructionStoreMemSize;
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68 | procedure InstructionLoadMemIndex;
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69 | procedure InstructionLoadMemIndexSize;
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70 | procedure InstructionStoreMemIndex;
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71 | procedure InstructionStoreMemIndexSize;
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72 | procedure InstructionJump;
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73 | procedure InstructionJumpSize;
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74 | procedure InstructionJumpNotZero;
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75 | procedure InstructionJumpNotZeroSize;
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76 | procedure InstructionJumpZero;
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77 | procedure InstructionJumpZeroSize;
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78 | procedure InstructionJumpRel;
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79 | procedure InstructionJumpRelSize;
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80 | procedure InstructionCall;
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81 | procedure InstructionCallSize;
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82 | procedure InstructionRet;
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83 | procedure InstructionRetSize;
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84 | procedure InstructionPush;
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85 | procedure InstructionPushSize;
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86 | procedure InstructionPop;
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87 | procedure InstructionPopSize;
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88 | procedure InstructionInput;
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89 | procedure InstructionInputSize;
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90 | procedure InstructionOutput;
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91 | procedure InstructionOutputSize;
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92 | procedure InstructionInc;
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93 | procedure InstructionIncSize;
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94 | procedure InstructionDec;
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95 | procedure InstructionDecSize;
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96 | procedure InstructionXor;
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97 | procedure InstructionXorSize;
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98 | procedure InstructionAnd;
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99 | procedure InstructionAndSize;
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100 | procedure InstructionOr;
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101 | procedure InstructionOrSize;
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102 | procedure InstructionAdd;
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103 | procedure InstructionAddSize;
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104 | procedure InstructionSub;
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105 | procedure InstructionSubSize;
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106 | procedure InitInstructions;
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107 | procedure SetRunning(AValue: Boolean);
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108 | procedure Run;
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109 | procedure Step;
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110 | public
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111 | Regs: array[TRegIndex] of TInt;
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112 | PC: TInt;
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113 | SP: TInt;
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114 | DataWidth: TIntSize;
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115 | AddressWidth: TIntSize;
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116 | Memory: TChannel;
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117 | IO: TChannel;
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118 | function Read(Size: TIntSize): TInt;
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119 | function ReadSize: TIntSize;
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120 | function ReadRegIndex: TRegIndex;
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121 | procedure Write(Size: TIntSize; Value: TInt);
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122 | procedure WriteInstruction(Instruction: TInstruction);
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123 | procedure WriteRegister(Reg: TRegIndex);
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124 | procedure Reset;
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125 | procedure Start;
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126 | procedure Stop;
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127 | constructor Create;
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128 | destructor Destroy; override;
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129 | property Ticks: QWord read FTicks;
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130 | property Running: Boolean read FRunning write SetRunning;
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131 | property Halted: Boolean read FHalted;
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132 | end;
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133 |
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134 | { TCpuThread }
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135 |
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136 | TCpuThread = class(TThread)
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137 | Cpu: TCpu;
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138 | procedure Execute; override;
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139 | end;
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140 |
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141 |
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142 | implementation
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143 |
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144 | { TCpuThread }
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145 |
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146 | procedure TCpuThread.Execute;
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147 | begin
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148 | repeat
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149 | if not Cpu.Halted then Cpu.Step
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150 | else Sleep(1);
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151 | //Cpu.CheckInterreupts;
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152 | until Terminated;
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153 | end;
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154 |
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155 | { TCpu }
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156 |
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157 | procedure TCpu.Push(Value: TInt; Size: TIntSize);
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158 | begin
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159 | SP := (SP - Size + Memory.GetSize) mod Memory.GetSize;
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160 | Memory.Write(SP, Size, Value);
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161 | end;
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162 |
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163 | function TCpu.Pop(Size: TIntSize): TInt;
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164 | begin
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165 | Result := Memory.Read(SP, Size);
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166 | SP := (SP + Size) mod Memory.GetSize;
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167 | end;
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168 |
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169 | procedure TCpu.InstructionNop;
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170 | begin
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171 | // Do nothing
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172 | end;
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173 |
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174 | procedure TCpu.InstructionHalt;
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175 | begin
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176 | FHalted := True;
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177 | end;
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178 |
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179 | procedure TCpu.InstructionLoadConst;
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180 | var
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181 | RegIndex: TRegIndex;
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182 | begin
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183 | RegIndex := ReadRegIndex;
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184 | Regs[RegIndex] := Read(DataWidth);
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185 | end;
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186 |
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187 | procedure TCpu.InstructionLoadConstSize;
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188 | var
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189 | RegIndex: TRegIndex;
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190 | DataSize: TIntSize;
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191 | begin
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192 | DataSize := ReadSize;
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193 | RegIndex := ReadRegIndex;
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194 | Regs[RegIndex] := Read(DataSize);
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195 | end;
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196 |
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197 | procedure TCpu.InstructionLoad;
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198 | var
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199 | RegIndex: TRegIndex;
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200 | RegIndex2: TRegIndex;
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201 | begin
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202 | RegIndex := ReadRegIndex;
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203 | RegIndex2 := ReadRegIndex;
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204 | Regs[RegIndex] := Regs[RegIndex2];
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205 | end;
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206 |
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207 | procedure TCpu.InstructionLoadSize;
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208 | var
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209 | DataSize: TIntSize;
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210 | RegIndex: TRegIndex;
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211 | RegIndex2: TRegIndex;
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212 | begin
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213 | DataSize := ReadSize;
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214 | RegIndex := ReadRegIndex;
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215 | RegIndex2 := ReadRegIndex;
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216 | Regs[RegIndex] := LimitSize(Regs[RegIndex2], DataSize);
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217 | end;
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218 |
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219 | procedure TCpu.InstructionLoadMem;
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220 | var
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221 | RegIndex1: TRegIndex;
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222 | RegIndex2: TRegIndex;
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223 | begin
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224 | RegIndex1 := ReadRegIndex;
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225 | RegIndex2 := ReadRegIndex;
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226 | Regs[RegIndex1] := Memory.Read(Regs[RegIndex2], DataWidth);
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227 | end;
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228 |
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229 | procedure TCpu.InstructionLoadMemSize;
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230 | var
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231 | DataSize: TIntSize;
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232 | RegIndex1: TRegIndex;
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233 | RegIndex2: TRegIndex;
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234 | begin
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235 | DataSize := ReadSize;
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236 | RegIndex1 := ReadRegIndex;
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237 | RegIndex2 := ReadRegIndex;
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238 | Regs[RegIndex1] := Memory.Read(Regs[RegIndex2], DataSize);
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239 | end;
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240 |
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241 | procedure TCpu.InstructionStoreMem;
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242 | var
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243 | RegIndex1: TRegIndex;
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244 | RegIndex2: TRegIndex;
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245 | begin
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246 | RegIndex1 := ReadRegIndex;
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247 | RegIndex2 := ReadRegIndex;
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248 | Memory.Write(Regs[RegIndex1], DataWidth, Regs[RegIndex2]);
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249 | end;
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250 |
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251 | procedure TCpu.InstructionStoreMemSize;
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252 | var
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253 | DataSize: TIntSize;
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254 | RegIndex1: TRegIndex;
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255 | RegIndex2: TRegIndex;
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256 | begin
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257 | DataSize := ReadSize;
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258 | RegIndex1 := ReadRegIndex;
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259 | RegIndex2 := ReadRegIndex;
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260 | Memory.Write(Regs[RegIndex1], DataSize, Regs[RegIndex2]);
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261 | end;
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262 |
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263 | procedure TCpu.InstructionLoadMemIndex;
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264 | var
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265 | RegIndex1: TRegIndex;
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266 | RegIndex2: TRegIndex;
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267 | RelativeAddress: TInt;
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268 | begin
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269 | RegIndex1 := ReadRegIndex;
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270 | RegIndex2 := ReadRegIndex;
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271 | RelativeAddress := Read(AddressWidth);
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272 | Regs[RegIndex1] := Memory.Read(Regs[RegIndex2] + RelativeAddress, DataWidth);
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273 | end;
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274 |
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275 | procedure TCpu.InstructionLoadMemIndexSize;
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276 | var
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277 | DataSize: TIntSize;
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278 | RegIndex1: TRegIndex;
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279 | RegIndex2: TRegIndex;
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280 | RelativeAddress: TInt;
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281 | begin
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282 | DataSize := ReadSize;
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283 | RegIndex1 := ReadRegIndex;
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284 | RegIndex2 := ReadRegIndex;
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285 | RelativeAddress := Read(AddressWidth);
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286 | Regs[RegIndex1] := Memory.Read(Regs[RegIndex2] + RelativeAddress, DataSize);
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287 | end;
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288 |
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289 | procedure TCpu.InstructionStoreMemIndex;
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290 | var
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291 | RegIndex1: TRegIndex;
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292 | RegIndex2: TRegIndex;
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293 | RelativeAddress: TInt;
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294 | begin
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295 | RegIndex1 := ReadRegIndex;
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296 | RegIndex2 := ReadRegIndex;
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297 | RelativeAddress := Read(AddressWidth);
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298 | Memory.Write(Regs[RegIndex1] + RelativeAddress, DataWidth, Regs[RegIndex2]);
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299 | end;
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300 |
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301 | procedure TCpu.InstructionStoreMemIndexSize;
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302 | var
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303 | DataSize: TIntSize;
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304 | RegIndex1: TRegIndex;
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305 | RegIndex2: TRegIndex;
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306 | RelativeAddress: TInt;
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307 | begin
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308 | DataSize := ReadSize;
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309 | RegIndex1 := ReadRegIndex;
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310 | RegIndex2 := ReadRegIndex;
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311 | RelativeAddress := Read(AddressWidth);
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312 | Memory.Write(Regs[RegIndex1] + RelativeAddress, DataSize, Regs[RegIndex2]);
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313 | end;
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314 |
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315 | procedure TCpu.InstructionJump;
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316 | begin
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317 | PC := Read(AddressWidth);
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318 | end;
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319 |
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320 | procedure TCpu.InstructionJumpSize;
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321 | var
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322 | AddressSize: TIntSize;
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323 | begin
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324 | AddressSize := Read(SizeOf(TIntSize));
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325 | PC := Read(AddressSize);
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326 | end;
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327 |
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328 | procedure TCpu.InstructionJumpNotZero;
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329 | var
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330 | RegIndex: TRegIndex;
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331 | Address: TInt;
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332 | begin
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333 | RegIndex := ReadRegIndex;
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334 | Address := Read(AddressWidth);
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335 | if Regs[RegIndex] <> 0 then
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336 | PC := Address;
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337 | end;
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338 |
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339 | procedure TCpu.InstructionJumpNotZeroSize;
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340 | var
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341 | RegIndex: TRegIndex;
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342 | Address: TInt;
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343 | DataSize: TIntSize;
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344 | AddressSize: TIntSize;
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345 | begin
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346 | DataSize := ReadSize;
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347 | AddressSize := Read(SizeOf(TIntSize));
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348 | RegIndex := ReadRegIndex;
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349 | Address := Read(AddressSize);
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350 | if LimitSize(Regs[RegIndex], DataSize) <> 0 then
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351 | PC := Address;
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352 | end;
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353 |
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354 | procedure TCpu.InstructionJumpZero;
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355 | var
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356 | RegIndex: TRegIndex;
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357 | Address: TInt;
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358 | begin
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359 | RegIndex := ReadRegIndex;
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360 | Address := Read(AddressWidth);
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361 | if Regs[RegIndex] = 0 then
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362 | PC := Address;
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363 | end;
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364 |
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365 | procedure TCpu.InstructionJumpZeroSize;
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366 | var
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367 | RegIndex: TRegIndex;
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368 | Address: TInt;
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369 | DataSize: TIntSize;
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370 | AddressSize: TIntSize;
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371 | begin
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372 | DataSize := ReadSize;
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373 | AddressSize := Read(SizeOf(TIntSize));
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374 | RegIndex := ReadRegIndex;
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375 | Address := Read(AddressSize);
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376 | if LimitSize(Regs[RegIndex], DataSize) = 0 then
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377 | PC := Address;
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378 | end;
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379 |
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380 | procedure TCpu.InstructionJumpRel;
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381 | begin
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382 | PC := PC + Read(AddressWidth);
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383 | end;
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384 |
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385 | procedure TCpu.InstructionJumpRelSize;
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386 | var
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387 | AddressSize: TIntSize;
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388 | begin
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389 | AddressSize := ReadSize;
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390 | PC := PC + Read(AddressSize);
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391 | end;
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392 |
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393 | procedure TCpu.InstructionCall;
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394 | var
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395 | NewAddress: TInt;
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396 | begin
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397 | NewAddress := Read(AddressWidth);
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398 | Push(PC, AddressWidth);
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399 | PC := NewAddress;
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400 | end;
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401 |
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402 | procedure TCpu.InstructionCallSize;
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403 | var
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404 | AddressSize: TIntSize;
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405 | begin
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406 | AddressSize := ReadSize;
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407 | Push(PC, AddressSize);
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408 | PC := Read(AddressSize);
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409 | end;
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410 |
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411 | procedure TCpu.InstructionRet;
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412 | begin
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413 | PC := Pop(AddressWidth);
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414 | end;
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415 |
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416 | procedure TCpu.InstructionRetSize;
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417 | var
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418 | AddressSize: TIntSize;
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419 | begin
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420 | AddressSize := ReadSize;
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421 | PC := Pop(AddressSize);
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422 | end;
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423 |
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424 | procedure TCpu.InstructionPush;
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425 | var
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426 | RegIndex: TRegIndex;
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427 | begin
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428 | RegIndex := ReadRegIndex;
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429 | Push(Regs[RegIndex], DataWidth);
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430 | end;
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431 |
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432 | procedure TCpu.InstructionPushSize;
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433 | var
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434 | DataSize: TIntSize;
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435 | RegIndex: TRegIndex;
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436 | begin
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437 | DataSize := ReadSize;
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438 | RegIndex := ReadRegIndex;
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439 | Push(Regs[RegIndex], DataSize);
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440 | end;
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441 |
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442 | procedure TCpu.InstructionPop;
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443 | var
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444 | RegIndex: TRegIndex;
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445 | begin
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446 | RegIndex := ReadRegIndex;
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447 | Regs[RegIndex] := Pop(DataWidth);
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448 | end;
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449 |
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450 | procedure TCpu.InstructionPopSize;
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451 | var
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452 | DataSize: TIntSize;
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453 | RegIndex: TRegIndex;
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454 | begin
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455 | DataSize := ReadSize;
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456 | RegIndex := ReadRegIndex;
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457 | Regs[RegIndex] := Pop(DataSize);
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458 | end;
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459 |
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460 | procedure TCpu.InstructionInput;
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461 | var
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462 | RegIndex: TRegIndex;
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463 | RegIndex2: TRegIndex;
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464 | begin
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465 | RegIndex := ReadRegIndex;
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466 | RegIndex2 := ReadRegIndex;
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467 | Regs[RegIndex] := IO.Read(Regs[RegIndex2], DataWidth);
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468 | end;
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469 |
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470 | procedure TCpu.InstructionInputSize;
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471 | var
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472 | RegIndex: TRegIndex;
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473 | RegIndex2: TRegIndex;
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474 | DataSize: TIntSize;
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475 | begin
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476 | DataSize := ReadSize;
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477 | RegIndex := ReadRegIndex;
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478 | RegIndex2 := ReadRegIndex;
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479 | Regs[RegIndex] := IO.Read(Regs[RegIndex2], DataSize);
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480 | end;
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481 |
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482 | procedure TCpu.InstructionOutput;
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483 | var
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484 | RegIndex: TRegIndex;
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485 | RegIndex2: TRegIndex;
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486 | begin
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487 | RegIndex := ReadRegIndex;
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488 | RegIndex2 := ReadRegIndex;
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489 | IO.Write(Regs[RegIndex], DataWidth, Regs[RegIndex2]);
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490 | end;
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491 |
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492 | procedure TCpu.InstructionOutputSize;
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493 | var
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494 | RegIndex: TRegIndex;
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495 | RegIndex2: TRegIndex;
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496 | DataSize: TIntSize;
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497 | begin
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498 | DataSize := ReadSize;
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499 | RegIndex := ReadRegIndex;
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500 | RegIndex2 := ReadRegIndex;
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501 | IO.Write(Regs[RegIndex], DataSize, Regs[RegIndex2]);
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502 | end;
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503 |
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504 | procedure TCpu.InstructionInc;
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505 | var
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506 | RegIndex: TRegIndex;
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507 | begin
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508 | RegIndex := ReadRegIndex;
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509 | Regs[RegIndex] := Regs[RegIndex] + 1;
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510 | end;
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511 |
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512 | procedure TCpu.InstructionIncSize;
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513 | var
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514 | RegIndex: TRegIndex;
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515 | DataSize: TIntSize;
|
---|
516 | begin
|
---|
517 | DataSize := ReadSize;
|
---|
518 | RegIndex := ReadRegIndex;
|
---|
519 | Regs[RegIndex] := LimitSize(Regs[RegIndex], DataSize) + 1;
|
---|
520 | end;
|
---|
521 |
|
---|
522 | procedure TCpu.InstructionDec;
|
---|
523 | var
|
---|
524 | RegIndex: TRegIndex;
|
---|
525 | begin
|
---|
526 | RegIndex := ReadRegIndex;
|
---|
527 | Regs[RegIndex] := Regs[RegIndex] - 1;
|
---|
528 | end;
|
---|
529 |
|
---|
530 | procedure TCpu.InstructionDecSize;
|
---|
531 | var
|
---|
532 | RegIndex: TRegIndex;
|
---|
533 | DataSize: TIntSize;
|
---|
534 | begin
|
---|
535 | DataSize := ReadSize;
|
---|
536 | RegIndex := ReadRegIndex;
|
---|
537 | Regs[RegIndex] := LimitSize(Regs[RegIndex], DataSize) - 1;
|
---|
538 | end;
|
---|
539 |
|
---|
540 | procedure TCpu.InstructionXor;
|
---|
541 | var
|
---|
542 | RegIndex: TRegIndex;
|
---|
543 | RegIndex2: TRegIndex;
|
---|
544 | begin
|
---|
545 | RegIndex := ReadRegIndex;
|
---|
546 | RegIndex2 := ReadRegIndex;
|
---|
547 | Regs[RegIndex] := Regs[RegIndex] xor Regs[RegIndex2];
|
---|
548 | end;
|
---|
549 |
|
---|
550 | procedure TCpu.InstructionXorSize;
|
---|
551 | var
|
---|
552 | DataSize: TIntSize;
|
---|
553 | RegIndex: TRegIndex;
|
---|
554 | RegIndex2: TRegIndex;
|
---|
555 | begin
|
---|
556 | DataSize := ReadSize;
|
---|
557 | RegIndex := ReadRegIndex;
|
---|
558 | RegIndex2 := ReadRegIndex;
|
---|
559 | Regs[RegIndex] := LimitSize(Regs[RegIndex] xor Regs[RegIndex2], DataSize);
|
---|
560 | end;
|
---|
561 |
|
---|
562 | procedure TCpu.InstructionAnd;
|
---|
563 | var
|
---|
564 | RegIndex: TRegIndex;
|
---|
565 | RegIndex2: TRegIndex;
|
---|
566 | begin
|
---|
567 | RegIndex := ReadRegIndex;
|
---|
568 | RegIndex2 := ReadRegIndex;
|
---|
569 | Regs[RegIndex] := Regs[RegIndex] and Regs[RegIndex2];
|
---|
570 | end;
|
---|
571 |
|
---|
572 | procedure TCpu.InstructionAndSize;
|
---|
573 | var
|
---|
574 | DataSize: TIntSize;
|
---|
575 | RegIndex: TRegIndex;
|
---|
576 | RegIndex2: TRegIndex;
|
---|
577 | begin
|
---|
578 | DataSize := ReadSize;
|
---|
579 | RegIndex := ReadRegIndex;
|
---|
580 | RegIndex2 := ReadRegIndex;
|
---|
581 | Regs[RegIndex] := LimitSize(Regs[RegIndex] and Regs[RegIndex2], DataSize);
|
---|
582 | end;
|
---|
583 |
|
---|
584 | procedure TCpu.InstructionOr;
|
---|
585 | var
|
---|
586 | RegIndex: TRegIndex;
|
---|
587 | RegIndex2: TRegIndex;
|
---|
588 | begin
|
---|
589 | RegIndex := ReadRegIndex;
|
---|
590 | RegIndex2 := ReadRegIndex;
|
---|
591 | Regs[RegIndex] := Regs[RegIndex] or Regs[RegIndex2];
|
---|
592 | end;
|
---|
593 |
|
---|
594 | procedure TCpu.InstructionOrSize;
|
---|
595 | var
|
---|
596 | DataSize: TIntSize;
|
---|
597 | RegIndex: TRegIndex;
|
---|
598 | RegIndex2: TRegIndex;
|
---|
599 | begin
|
---|
600 | DataSize := ReadSize;
|
---|
601 | RegIndex := ReadRegIndex;
|
---|
602 | RegIndex2 := ReadRegIndex;
|
---|
603 | Regs[RegIndex] := LimitSize(Regs[RegIndex] or Regs[RegIndex2], DataSize);
|
---|
604 | end;
|
---|
605 |
|
---|
606 | procedure TCpu.InstructionAdd;
|
---|
607 | var
|
---|
608 | RegIndex: TRegIndex;
|
---|
609 | RegIndex2: TRegIndex;
|
---|
610 | begin
|
---|
611 | RegIndex := ReadRegIndex;
|
---|
612 | RegIndex2 := ReadRegIndex;
|
---|
613 | Regs[RegIndex] := Regs[RegIndex] + Regs[RegIndex2];
|
---|
614 | end;
|
---|
615 |
|
---|
616 | procedure TCpu.InstructionAddSize;
|
---|
617 | var
|
---|
618 | DataSize: TIntSize;
|
---|
619 | RegIndex: TRegIndex;
|
---|
620 | RegIndex2: TRegIndex;
|
---|
621 | begin
|
---|
622 | DataSize := ReadSize;
|
---|
623 | RegIndex := ReadRegIndex;
|
---|
624 | RegIndex2 := ReadRegIndex;
|
---|
625 | Regs[RegIndex] := LimitSize(Regs[RegIndex] + Regs[RegIndex2], DataSize);
|
---|
626 | end;
|
---|
627 |
|
---|
628 | procedure TCpu.InstructionSub;
|
---|
629 | var
|
---|
630 | RegIndex: TRegIndex;
|
---|
631 | RegIndex2: TRegIndex;
|
---|
632 | begin
|
---|
633 | RegIndex := ReadRegIndex;
|
---|
634 | RegIndex2 := ReadRegIndex;
|
---|
635 | Regs[RegIndex] := Regs[RegIndex] - Regs[RegIndex2];
|
---|
636 | end;
|
---|
637 |
|
---|
638 | procedure TCpu.InstructionSubSize;
|
---|
639 | var
|
---|
640 | DataSize: TIntSize;
|
---|
641 | RegIndex: TRegIndex;
|
---|
642 | RegIndex2: TRegIndex;
|
---|
643 | begin
|
---|
644 | DataSize := ReadSize;
|
---|
645 | RegIndex := ReadRegIndex;
|
---|
646 | RegIndex2 := ReadRegIndex;
|
---|
647 | Regs[RegIndex] := LimitSize(Regs[RegIndex] + Regs[RegIndex2], DataSize);
|
---|
648 | end;
|
---|
649 |
|
---|
650 | procedure TCpu.InitInstructions;
|
---|
651 | begin
|
---|
652 | FInstructions[inNop] := InstructionNop;
|
---|
653 | FInstructions[inHalt] := InstructionHalt;
|
---|
654 | FInstructions[inLoadConst] := InstructionLoadConst;
|
---|
655 | FInstructions[inLoadConstSize] := InstructionLoadConstSize;
|
---|
656 | FInstructions[inLoad] := InstructionLoad;
|
---|
657 | FInstructions[inLoadSize] := InstructionLoadSize;
|
---|
658 | FInstructions[inLoadMem] := InstructionLoadMem;
|
---|
659 | FInstructions[inLoadMemSize] := InstructionLoadMemSize;
|
---|
660 | FInstructions[inStoreMem] := InstructionStoreMem;
|
---|
661 | FInstructions[inStoreMemSize] := InstructionStoreMemSize;
|
---|
662 | FInstructions[inLoadMemIndex] := InstructionLoadMemIndex;
|
---|
663 | FInstructions[inLoadMemIndexSize] := InstructionLoadMemIndexSize;
|
---|
664 | FInstructions[inStoreMemIndex] := InstructionStoreMemIndex;
|
---|
665 | FInstructions[inStoreMemIndexSize] := InstructionStoreMemIndexSize;
|
---|
666 | FInstructions[inJump] := InstructionJump;
|
---|
667 | FInstructions[inJumpSize] := InstructionJumpSize;
|
---|
668 | FInstructions[inJumpNotZero] := InstructionJumpNotZero;
|
---|
669 | FInstructions[inJumpNotZeroSize] := InstructionJumpNotZeroSize;
|
---|
670 | FInstructions[inJumpZero] := InstructionJumpZero;
|
---|
671 | FInstructions[inJumpZeroSize] := InstructionJumpZeroSize;
|
---|
672 | FInstructions[inJumpRel] := InstructionJumpRel;
|
---|
673 | FInstructions[inJumpRelSize] := InstructionJumpRelSize;
|
---|
674 | FInstructions[inCall] := InstructionCall;
|
---|
675 | FInstructions[inCallSize] := InstructionCallSize;
|
---|
676 | FInstructions[inRet] := InstructionRet;
|
---|
677 | FInstructions[inRetSize] := InstructionRetSize;
|
---|
678 | FInstructions[inPush] := InstructionPush;
|
---|
679 | FInstructions[inPushSize] := InstructionPushSize;
|
---|
680 | FInstructions[inPop] := InstructionPop;
|
---|
681 | FInstructions[inPopSize] := InstructionPopSize;
|
---|
682 | FInstructions[inInput] := InstructionInput;
|
---|
683 | FInstructions[inInputSize] := InstructionInputSize;
|
---|
684 | FInstructions[inOutput] := InstructionOutput;
|
---|
685 | FInstructions[inOutputSize] := InstructionOutputSize;
|
---|
686 | FInstructions[inInc] := InstructionInc;
|
---|
687 | FInstructions[inIncSize] := InstructionIncSize;
|
---|
688 | FInstructions[inDec] := InstructionDec;
|
---|
689 | FInstructions[inDecSize] := InstructionDecSize;
|
---|
690 | FInstructions[inXor] := InstructionXor;
|
---|
691 | FInstructions[inXorSize] := InstructionXorSize;
|
---|
692 | FInstructions[inAnd] := InstructionAnd;
|
---|
693 | FInstructions[inAndSize] := InstructionAndSize;
|
---|
694 | FInstructions[inOr] := InstructionOr;
|
---|
695 | FInstructions[inOrSize] := InstructionOrSize;
|
---|
696 | FInstructions[inAdd] := InstructionAdd;
|
---|
697 | FInstructions[inAddSize] := InstructionAddSize;
|
---|
698 | FInstructions[inSub] := InstructionSub;
|
---|
699 | FInstructions[inSubSize] := InstructionSubSize;
|
---|
700 | end;
|
---|
701 |
|
---|
702 | procedure TCpu.SetRunning(AValue: Boolean);
|
---|
703 | begin
|
---|
704 | if FRunning = AValue then Exit;
|
---|
705 | if AValue then Start
|
---|
706 | else Stop;
|
---|
707 | end;
|
---|
708 |
|
---|
709 | function TCpu.Read(Size: TIntSize): TInt;
|
---|
710 | begin
|
---|
711 | Result := Memory.Read(PC, Size);
|
---|
712 | PC := PC + Size;
|
---|
713 | end;
|
---|
714 |
|
---|
715 | function TCpu.ReadSize: TIntSize;
|
---|
716 | begin
|
---|
717 | Result := Read(SizeOf(TIntSize));
|
---|
718 | end;
|
---|
719 |
|
---|
720 | function TCpu.ReadRegIndex: TRegIndex;
|
---|
721 | begin
|
---|
722 | Result := TRegIndex(Byte(Read(1)));
|
---|
723 | end;
|
---|
724 |
|
---|
725 | procedure TCpu.Write(Size: TIntSize; Value: TInt);
|
---|
726 | begin
|
---|
727 | Memory.Write(PC, Size, Value);
|
---|
728 | PC := PC + Size;
|
---|
729 | end;
|
---|
730 |
|
---|
731 | procedure TCpu.WriteInstruction(Instruction: TInstruction);
|
---|
732 | begin
|
---|
733 | Write(1, Byte(Instruction));
|
---|
734 | end;
|
---|
735 |
|
---|
736 | procedure TCpu.WriteRegister(Reg: TRegIndex);
|
---|
737 | begin
|
---|
738 | Write(1, Byte(Reg));
|
---|
739 | end;
|
---|
740 |
|
---|
741 | procedure TCpu.Reset;
|
---|
742 | var
|
---|
743 | I: TRegIndex;
|
---|
744 | begin
|
---|
745 | DataWidth := 2;
|
---|
746 | AddressWidth := 2;
|
---|
747 | for I := Low(TRegIndex) to High(TRegIndex) do
|
---|
748 | Regs[I] := 0;
|
---|
749 | PC := 0;
|
---|
750 | SP := 0;
|
---|
751 | FHalted := False;
|
---|
752 | FTicks := 0;
|
---|
753 | end;
|
---|
754 |
|
---|
755 | procedure TCpu.Run;
|
---|
756 | begin
|
---|
757 | Reset;
|
---|
758 | while not FHalted do
|
---|
759 | Step;
|
---|
760 | end;
|
---|
761 |
|
---|
762 | procedure TCpu.Step;
|
---|
763 | var
|
---|
764 | Instruction: TInstruction;
|
---|
765 | begin
|
---|
766 | Instruction := TInstruction(Byte(Read(1)));
|
---|
767 | FInstructions[Instruction];
|
---|
768 | Inc(FTicks);
|
---|
769 | end;
|
---|
770 |
|
---|
771 | procedure TCpu.Start;
|
---|
772 | begin
|
---|
773 | if not Running then begin
|
---|
774 | Reset;
|
---|
775 | FThread := TCpuThread.Create(True);
|
---|
776 | FThread.Cpu := Self;
|
---|
777 | FThread.Start;
|
---|
778 | FRunning := True;
|
---|
779 | end;
|
---|
780 | end;
|
---|
781 |
|
---|
782 | procedure TCpu.Stop;
|
---|
783 | begin
|
---|
784 | if Running then begin
|
---|
785 | FHalted := True;
|
---|
786 | FThread.Terminate;
|
---|
787 | FThread.WaitFor;
|
---|
788 | FreeAndNil(FThread);
|
---|
789 | FRunning := False;
|
---|
790 | end;
|
---|
791 | end;
|
---|
792 |
|
---|
793 | constructor TCpu.Create;
|
---|
794 | begin
|
---|
795 | Memory := TChannel.Create;
|
---|
796 | IO := TChannel.Create;
|
---|
797 | InitInstructions;
|
---|
798 | Reset;
|
---|
799 | end;
|
---|
800 |
|
---|
801 | destructor TCpu.Destroy;
|
---|
802 | begin
|
---|
803 | Stop;
|
---|
804 | FreeAndNil(Memory);
|
---|
805 | FreeAndNil(IO);
|
---|
806 | inherited;
|
---|
807 | end;
|
---|
808 |
|
---|
809 | end.
|
---|
810 |
|
---|